linux-headers (unknown)
1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2 /*
3 * linux/drivers/char/serial_core.h
4 *
5 * Copyright (C) 2000 Deep Blue Solutions Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21 #ifndef LINUX_SERIAL_CORE_H
22 #define LINUX_SERIAL_CORE_H
23
24 #include <linux/serial.h>
25
26 /*
27 * The type definitions. These are from Ted Ts'o's serial.h
28 */
29 #define PORT_NS16550A 14
30 #define PORT_XSCALE 15
31 #define PORT_RM9000 16 /* PMC-Sierra RM9xxx internal UART */
32 #define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
33 #define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
34 #define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
35 #define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
36 #define PORT_XR17D15X 21 /* Exar XR17D15x UART */
37 #define PORT_LPC3220 22 /* NXP LPC32xx SoC "Standard" UART */
38 #define PORT_8250_CIR 23 /* CIR infrared port, has its own driver */
39 #define PORT_XR17V35X 24 /* Exar XR17V35x UARTs */
40 #define PORT_BRCM_TRUMANAGE 25
41 #define PORT_ALTR_16550_F32 26 /* Altera 16550 UART with 32 FIFOs */
42 #define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
43 #define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
44 #define PORT_RT2880 29 /* Ralink RT2880 internal UART */
45 #define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
46
47 /*
48 * ARM specific type numbers. These are not currently guaranteed
49 * to be implemented, and will change in the future. These are
50 * separate so any additions to the old serial.c that occur before
51 * we are merged can be easily merged here.
52 */
53 #define PORT_PXA 31
54 #define PORT_AMBA 32
55 #define PORT_CLPS711X 33
56 #define PORT_SA1100 34
57 #define PORT_UART00 35
58 #define PORT_OWL 36
59 #define PORT_21285 37
60
61 /* Sparc type numbers. */
62 #define PORT_SUNZILOG 38
63 #define PORT_SUNSAB 39
64
65 /* Nuvoton UART */
66 #define PORT_NPCM 40
67
68 /* NVIDIA Tegra Combined UART */
69 #define PORT_TEGRA_TCU 41
70
71 /* ASPEED AST2x00 virtual UART */
72 #define PORT_ASPEED_VUART 42
73
74 /* Intel EG20 */
75 #define PORT_PCH_8LINE 44
76 #define PORT_PCH_2LINE 45
77
78 /* DEC */
79 #define PORT_DZ 46
80 #define PORT_ZS 47
81
82 /* Parisc type numbers. */
83 #define PORT_MUX 48
84
85 /* Atmel AT91 SoC */
86 #define PORT_ATMEL 49
87
88 /* Macintosh Zilog type numbers */
89 #define PORT_MAC_ZILOG 50 /* m68k : not yet implemented */
90 #define PORT_PMAC_ZILOG 51
91
92 /* SH-SCI */
93 #define PORT_SCI 52
94 #define PORT_SCIF 53
95 #define PORT_IRDA 54
96
97 /* Samsung S3C2410 SoC and derivatives thereof */
98 #define PORT_S3C2410 55
99
100 /* SGI IP22 aka Indy / Challenge S / Indigo 2 */
101 #define PORT_IP22ZILOG 56
102
103 /* Sharp LH7a40x -- an ARM9 SoC series */
104 #define PORT_LH7A40X 57
105
106 /* PPC CPM type number */
107 #define PORT_CPM 58
108
109 /* MPC52xx (and MPC512x) type numbers */
110 #define PORT_MPC52xx 59
111
112 /* IBM icom */
113 #define PORT_ICOM 60
114
115 /* Samsung S3C2440 SoC */
116 #define PORT_S3C2440 61
117
118 /* Motorola i.MX SoC */
119 #define PORT_IMX 62
120
121 /* Marvell MPSC (obsolete unused) */
122 #define PORT_MPSC 63
123
124 /* TXX9 type number */
125 #define PORT_TXX9 64
126
127 /* Samsung S3C2400 SoC */
128 #define PORT_S3C2400 67
129
130 /* M32R SIO */
131 #define PORT_M32R_SIO 68
132
133 /*Digi jsm */
134 #define PORT_JSM 69
135
136 /* SUN4V Hypervisor Console */
137 #define PORT_SUNHV 72
138
139 #define PORT_S3C2412 73
140
141 /* Xilinx uartlite */
142 #define PORT_UARTLITE 74
143
144 /* Blackfin bf5xx */
145 #define PORT_BFIN 75
146
147 /* Broadcom SB1250, etc. SOC */
148 #define PORT_SB1250_DUART 77
149
150 /* Freescale ColdFire */
151 #define PORT_MCF 78
152
153 /* Blackfin SPORT */
154 #define PORT_BFIN_SPORT 79
155
156 /* MN10300 on-chip UART numbers */
157 #define PORT_MN10300 80
158 #define PORT_MN10300_CTS 81
159
160 #define PORT_SC26XX 82
161
162 /* SH-SCI */
163 #define PORT_SCIFA 83
164
165 #define PORT_S3C6400 84
166
167 /* NWPSERIAL, now removed */
168 #define PORT_NWPSERIAL 85
169
170 /* MAX3100 */
171 #define PORT_MAX3100 86
172
173 /* Timberdale UART */
174 #define PORT_TIMBUART 87
175
176 /* Qualcomm MSM SoCs */
177 #define PORT_MSM 88
178
179 /* BCM63xx family SoCs */
180 #define PORT_BCM63XX 89
181
182 /* Aeroflex Gaisler GRLIB APBUART */
183 #define PORT_APBUART 90
184
185 /* Altera UARTs */
186 #define PORT_ALTERA_JTAGUART 91
187 #define PORT_ALTERA_UART 92
188
189 /* SH-SCI */
190 #define PORT_SCIFB 93
191
192 /* MAX310X */
193 #define PORT_MAX310X 94
194
195 /* TI DA8xx/66AK2x */
196 #define PORT_DA830 95
197
198 /* TI OMAP-UART */
199 #define PORT_OMAP 96
200
201 /* VIA VT8500 SoC */
202 #define PORT_VT8500 97
203
204 /* Cadence (Xilinx Zynq) UART */
205 #define PORT_XUARTPS 98
206
207 /* Atheros AR933X SoC */
208 #define PORT_AR933X 99
209
210 /* MCHP 16550A UART with 256 byte FIFOs */
211 #define PORT_MCHP16550A 100
212
213 /* ARC (Synopsys) on-chip UART */
214 #define PORT_ARC 101
215
216 /* Rocketport EXPRESS/INFINITY */
217 #define PORT_RP2 102
218
219 /* Freescale lpuart */
220 #define PORT_LPUART 103
221
222 /* SH-SCI */
223 #define PORT_HSCIF 104
224
225 /* ST ASC type numbers */
226 #define PORT_ASC 105
227
228 /* Tilera TILE-Gx UART */
229 #define PORT_TILEGX 106
230
231 /* MEN 16z135 UART */
232 #define PORT_MEN_Z135 107
233
234 /* SC16IS74xx */
235 #define PORT_SC16IS7XX 108
236
237 /* MESON */
238 #define PORT_MESON 109
239
240 /* Conexant Digicolor */
241 #define PORT_DIGICOLOR 110
242
243 /* SPRD SERIAL */
244 #define PORT_SPRD 111
245
246 /* Cris v10 / v32 SoC */
247 #define PORT_CRIS 112
248
249 /* STM32 USART */
250 #define PORT_STM32 113
251
252 /* MVEBU UART */
253 #define PORT_MVEBU 114
254
255 /* Microchip PIC32 UART */
256 #define PORT_PIC32 115
257
258 /* MPS2 UART */
259 #define PORT_MPS2UART 116
260
261 /* MediaTek BTIF */
262 #define PORT_MTK_BTIF 117
263
264 /* RDA UART */
265 #define PORT_RDA 118
266
267 /* Socionext Milbeaut UART */
268 #define PORT_MLB_USIO 119
269
270 /* SiFive UART */
271 #define PORT_SIFIVE_V0 120
272
273 /* Sunix UART */
274 #define PORT_SUNIX 121
275
276 /* Freescale LINFlexD UART */
277 #define PORT_LINFLEXUART 122
278
279 /* Sunplus UART */
280 #define PORT_SUNPLUS 123
281
282 #endif /* LINUX_SERIAL_CORE_H */
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