linux-headers (unknown)
1 /* SPDX-License-Identifier: LGPL-2.1 WITH Linux-syscall-note */
2 /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
3 #ifndef _USR_IDXD_H_
4 #define _USR_IDXD_H_
5
6 #include <stdint.h>
7
8 /* Driver command error status */
9 enum idxd_scmd_stat {
10 IDXD_SCMD_DEV_ENABLED = 0x80000010,
11 IDXD_SCMD_DEV_NOT_ENABLED = 0x80000020,
12 IDXD_SCMD_WQ_ENABLED = 0x80000021,
13 IDXD_SCMD_DEV_DMA_ERR = 0x80020000,
14 IDXD_SCMD_WQ_NO_GRP = 0x80030000,
15 IDXD_SCMD_WQ_NO_NAME = 0x80040000,
16 IDXD_SCMD_WQ_NO_SVM = 0x80050000,
17 IDXD_SCMD_WQ_NO_THRESH = 0x80060000,
18 IDXD_SCMD_WQ_PORTAL_ERR = 0x80070000,
19 IDXD_SCMD_WQ_RES_ALLOC_ERR = 0x80080000,
20 IDXD_SCMD_PERCPU_ERR = 0x80090000,
21 IDXD_SCMD_DMA_CHAN_ERR = 0x800a0000,
22 IDXD_SCMD_CDEV_ERR = 0x800b0000,
23 IDXD_SCMD_WQ_NO_SWQ_SUPPORT = 0x800c0000,
24 IDXD_SCMD_WQ_NONE_CONFIGURED = 0x800d0000,
25 IDXD_SCMD_WQ_NO_SIZE = 0x800e0000,
26 IDXD_SCMD_WQ_NO_PRIV = 0x800f0000,
27 IDXD_SCMD_WQ_IRQ_ERR = 0x80100000,
28 IDXD_SCMD_WQ_USER_NO_IOMMU = 0x80110000,
29 IDXD_SCMD_DEV_EVL_ERR = 0x80120000,
30 };
31
32 #define IDXD_SCMD_SOFTERR_MASK 0x80000000
33 #define IDXD_SCMD_SOFTERR_SHIFT 16
34
35 /* Descriptor flags */
36 #define IDXD_OP_FLAG_FENCE 0x0001
37 #define IDXD_OP_FLAG_BOF 0x0002
38 #define IDXD_OP_FLAG_CRAV 0x0004
39 #define IDXD_OP_FLAG_RCR 0x0008
40 #define IDXD_OP_FLAG_RCI 0x0010
41 #define IDXD_OP_FLAG_CRSTS 0x0020
42 #define IDXD_OP_FLAG_CR 0x0080
43 #define IDXD_OP_FLAG_CC 0x0100
44 #define IDXD_OP_FLAG_ADDR1_TCS 0x0200
45 #define IDXD_OP_FLAG_ADDR2_TCS 0x0400
46 #define IDXD_OP_FLAG_ADDR3_TCS 0x0800
47 #define IDXD_OP_FLAG_CR_TCS 0x1000
48 #define IDXD_OP_FLAG_STORD 0x2000
49 #define IDXD_OP_FLAG_DRDBK 0x4000
50 #define IDXD_OP_FLAG_DSTS 0x8000
51
52 /* IAX */
53 #define IDXD_OP_FLAG_RD_SRC2_AECS 0x010000
54 #define IDXD_OP_FLAG_RD_SRC2_2ND 0x020000
55 #define IDXD_OP_FLAG_WR_SRC2_AECS_COMP 0x040000
56 #define IDXD_OP_FLAG_WR_SRC2_AECS_OVFL 0x080000
57 #define IDXD_OP_FLAG_SRC2_STS 0x100000
58 #define IDXD_OP_FLAG_CRC_RFC3720 0x200000
59
60 /* Opcode */
61 enum dsa_opcode {
62 DSA_OPCODE_NOOP = 0,
63 DSA_OPCODE_BATCH,
64 DSA_OPCODE_DRAIN,
65 DSA_OPCODE_MEMMOVE,
66 DSA_OPCODE_MEMFILL,
67 DSA_OPCODE_COMPARE,
68 DSA_OPCODE_COMPVAL,
69 DSA_OPCODE_CR_DELTA,
70 DSA_OPCODE_AP_DELTA,
71 DSA_OPCODE_DUALCAST,
72 DSA_OPCODE_TRANSL_FETCH,
73 DSA_OPCODE_CRCGEN = 0x10,
74 DSA_OPCODE_COPY_CRC,
75 DSA_OPCODE_DIF_CHECK,
76 DSA_OPCODE_DIF_INS,
77 DSA_OPCODE_DIF_STRP,
78 DSA_OPCODE_DIF_UPDT,
79 DSA_OPCODE_DIX_GEN = 0x17,
80 DSA_OPCODE_CFLUSH = 0x20,
81 };
82
83 enum iax_opcode {
84 IAX_OPCODE_NOOP = 0,
85 IAX_OPCODE_DRAIN = 2,
86 IAX_OPCODE_MEMMOVE,
87 IAX_OPCODE_DECOMPRESS = 0x42,
88 IAX_OPCODE_COMPRESS,
89 IAX_OPCODE_CRC64,
90 IAX_OPCODE_ZERO_DECOMP_32 = 0x48,
91 IAX_OPCODE_ZERO_DECOMP_16,
92 IAX_OPCODE_ZERO_COMP_32 = 0x4c,
93 IAX_OPCODE_ZERO_COMP_16,
94 IAX_OPCODE_SCAN = 0x50,
95 IAX_OPCODE_SET_MEMBER,
96 IAX_OPCODE_EXTRACT,
97 IAX_OPCODE_SELECT,
98 IAX_OPCODE_RLE_BURST,
99 IAX_OPCODE_FIND_UNIQUE,
100 IAX_OPCODE_EXPAND,
101 };
102
103 /* Completion record status */
104 enum dsa_completion_status {
105 DSA_COMP_NONE = 0,
106 DSA_COMP_SUCCESS,
107 DSA_COMP_SUCCESS_PRED,
108 DSA_COMP_PAGE_FAULT_NOBOF,
109 DSA_COMP_PAGE_FAULT_IR,
110 DSA_COMP_BATCH_FAIL,
111 DSA_COMP_BATCH_PAGE_FAULT,
112 DSA_COMP_DR_OFFSET_NOINC,
113 DSA_COMP_DR_OFFSET_ERANGE,
114 DSA_COMP_DIF_ERR,
115 DSA_COMP_BAD_OPCODE = 0x10,
116 DSA_COMP_INVALID_FLAGS,
117 DSA_COMP_NOZERO_RESERVE,
118 DSA_COMP_XFER_ERANGE,
119 DSA_COMP_DESC_CNT_ERANGE,
120 DSA_COMP_DR_ERANGE,
121 DSA_COMP_OVERLAP_BUFFERS,
122 DSA_COMP_DCAST_ERR,
123 DSA_COMP_DESCLIST_ALIGN,
124 DSA_COMP_INT_HANDLE_INVAL,
125 DSA_COMP_CRA_XLAT,
126 DSA_COMP_CRA_ALIGN,
127 DSA_COMP_ADDR_ALIGN,
128 DSA_COMP_PRIV_BAD,
129 DSA_COMP_TRAFFIC_CLASS_CONF,
130 DSA_COMP_PFAULT_RDBA,
131 DSA_COMP_HW_ERR1,
132 DSA_COMP_HW_ERR_DRB,
133 DSA_COMP_TRANSLATION_FAIL,
134 DSA_COMP_DRAIN_EVL = 0x26,
135 DSA_COMP_BATCH_EVL_ERR,
136 };
137
138 enum iax_completion_status {
139 IAX_COMP_NONE = 0,
140 IAX_COMP_SUCCESS,
141 IAX_COMP_PAGE_FAULT_IR = 0x04,
142 IAX_COMP_ANALYTICS_ERROR = 0x0a,
143 IAX_COMP_OUTBUF_OVERFLOW,
144 IAX_COMP_BAD_OPCODE = 0x10,
145 IAX_COMP_INVALID_FLAGS,
146 IAX_COMP_NOZERO_RESERVE,
147 IAX_COMP_INVALID_SIZE,
148 IAX_COMP_OVERLAP_BUFFERS = 0x16,
149 IAX_COMP_INT_HANDLE_INVAL = 0x19,
150 IAX_COMP_CRA_XLAT,
151 IAX_COMP_CRA_ALIGN,
152 IAX_COMP_ADDR_ALIGN,
153 IAX_COMP_PRIV_BAD,
154 IAX_COMP_TRAFFIC_CLASS_CONF,
155 IAX_COMP_PFAULT_RDBA,
156 IAX_COMP_HW_ERR1,
157 IAX_COMP_HW_ERR_DRB,
158 IAX_COMP_TRANSLATION_FAIL,
159 IAX_COMP_PRS_TIMEOUT,
160 IAX_COMP_WATCHDOG,
161 IAX_COMP_INVALID_COMP_FLAG = 0x30,
162 IAX_COMP_INVALID_FILTER_FLAG,
163 IAX_COMP_INVALID_INPUT_SIZE,
164 IAX_COMP_INVALID_NUM_ELEMS,
165 IAX_COMP_INVALID_SRC1_WIDTH,
166 IAX_COMP_INVALID_INVERT_OUT,
167 };
168
169 #define DSA_COMP_STATUS_MASK 0x7f
170 #define DSA_COMP_STATUS_WRITE 0x80
171 #define DSA_COMP_STATUS(status) ((status) & DSA_COMP_STATUS_MASK)
172
173 struct dsa_hw_desc {
174 uint32_t pasid:20;
175 uint32_t rsvd:11;
176 uint32_t priv:1;
177 uint32_t flags:24;
178 uint32_t opcode:8;
179 uint64_t completion_addr;
180 union {
181 uint64_t src_addr;
182 uint64_t rdback_addr;
183 uint64_t pattern;
184 uint64_t desc_list_addr;
185 uint64_t pattern_lower;
186 uint64_t transl_fetch_addr;
187 };
188 union {
189 uint64_t dst_addr;
190 uint64_t rdback_addr2;
191 uint64_t src2_addr;
192 uint64_t comp_pattern;
193 };
194 union {
195 uint32_t xfer_size;
196 uint32_t desc_count;
197 uint32_t region_size;
198 };
199 uint16_t int_handle;
200 uint16_t rsvd1;
201 union {
202 uint8_t expected_res;
203 /* create delta record */
204 struct {
205 uint64_t delta_addr;
206 uint32_t max_delta_size;
207 uint32_t delt_rsvd;
208 uint8_t expected_res_mask;
209 };
210 uint32_t delta_rec_size;
211 uint64_t dest2;
212 /* CRC */
213 struct {
214 uint32_t crc_seed;
215 uint32_t crc_rsvd;
216 uint64_t seed_addr;
217 };
218 /* DIF check or strip */
219 struct {
220 uint8_t src_dif_flags;
221 uint8_t dif_chk_res;
222 uint8_t dif_chk_flags;
223 uint8_t dif_chk_res2[5];
224 uint32_t chk_ref_tag_seed;
225 uint16_t chk_app_tag_mask;
226 uint16_t chk_app_tag_seed;
227 };
228 /* DIF insert */
229 struct {
230 uint8_t dif_ins_res;
231 uint8_t dest_dif_flag;
232 uint8_t dif_ins_flags;
233 uint8_t dif_ins_res2[13];
234 uint32_t ins_ref_tag_seed;
235 uint16_t ins_app_tag_mask;
236 uint16_t ins_app_tag_seed;
237 };
238 /* DIF update */
239 struct {
240 uint8_t src_upd_flags;
241 uint8_t upd_dest_flags;
242 uint8_t dif_upd_flags;
243 uint8_t dif_upd_res[5];
244 uint32_t src_ref_tag_seed;
245 uint16_t src_app_tag_mask;
246 uint16_t src_app_tag_seed;
247 uint32_t dest_ref_tag_seed;
248 uint16_t dest_app_tag_mask;
249 uint16_t dest_app_tag_seed;
250 };
251
252 /* Fill */
253 uint64_t pattern_upper;
254
255 /* Translation fetch */
256 struct {
257 uint64_t transl_fetch_res;
258 uint32_t region_stride;
259 };
260
261 /* DIX generate */
262 struct {
263 uint8_t dix_gen_res;
264 uint8_t dest_dif_flags;
265 uint8_t dif_flags;
266 uint8_t dix_gen_res2[13];
267 uint32_t ref_tag_seed;
268 uint16_t app_tag_mask;
269 uint16_t app_tag_seed;
270 };
271
272 uint8_t op_specific[24];
273 };
274 } __attribute__((packed));
275
276 struct iax_hw_desc {
277 uint32_t pasid:20;
278 uint32_t rsvd:11;
279 uint32_t priv:1;
280 uint32_t flags:24;
281 uint32_t opcode:8;
282 uint64_t completion_addr;
283 uint64_t src1_addr;
284 uint64_t dst_addr;
285 uint32_t src1_size;
286 uint16_t int_handle;
287 union {
288 uint16_t compr_flags;
289 uint16_t decompr_flags;
290 };
291 uint64_t src2_addr;
292 uint32_t max_dst_size;
293 uint32_t src2_size;
294 uint32_t filter_flags;
295 uint32_t num_inputs;
296 } __attribute__((packed));
297
298 struct dsa_raw_desc {
299 uint64_t field[8];
300 } __attribute__((packed));
301
302 /*
303 * The status field will be modified by hardware, therefore it should be
304 * __volatile__ and prevent the compiler from optimize the read.
305 */
306 struct dsa_completion_record {
307 __volatile__ uint8_t status;
308 union {
309 uint8_t result;
310 uint8_t dif_status;
311 };
312 uint8_t fault_info;
313 uint8_t rsvd;
314 union {
315 uint32_t bytes_completed;
316 uint32_t descs_completed;
317 };
318 uint64_t fault_addr;
319 union {
320 /* common record */
321 struct {
322 uint32_t invalid_flags:24;
323 uint32_t rsvd2:8;
324 };
325
326 uint32_t delta_rec_size;
327 uint64_t crc_val;
328
329 /* DIF check & strip */
330 struct {
331 uint32_t dif_chk_ref_tag;
332 uint16_t dif_chk_app_tag_mask;
333 uint16_t dif_chk_app_tag;
334 };
335
336 /* DIF insert */
337 struct {
338 uint64_t dif_ins_res;
339 uint32_t dif_ins_ref_tag;
340 uint16_t dif_ins_app_tag_mask;
341 uint16_t dif_ins_app_tag;
342 };
343
344 /* DIF update */
345 struct {
346 uint32_t dif_upd_src_ref_tag;
347 uint16_t dif_upd_src_app_tag_mask;
348 uint16_t dif_upd_src_app_tag;
349 uint32_t dif_upd_dest_ref_tag;
350 uint16_t dif_upd_dest_app_tag_mask;
351 uint16_t dif_upd_dest_app_tag;
352 };
353
354 /* DIX generate */
355 struct {
356 uint64_t dix_gen_res;
357 uint32_t dix_ref_tag;
358 uint16_t dix_app_tag_mask;
359 uint16_t dix_app_tag;
360 };
361
362 uint8_t op_specific[16];
363 };
364 } __attribute__((packed));
365
366 struct dsa_raw_completion_record {
367 uint64_t field[4];
368 } __attribute__((packed));
369
370 struct iax_completion_record {
371 __volatile__ uint8_t status;
372 uint8_t error_code;
373 uint8_t fault_info;
374 uint8_t rsvd;
375 uint32_t bytes_completed;
376 uint64_t fault_addr;
377 uint32_t invalid_flags;
378 uint32_t rsvd2;
379 uint32_t output_size;
380 uint8_t output_bits;
381 uint8_t rsvd3;
382 uint16_t xor_csum;
383 uint32_t crc;
384 uint32_t min;
385 uint32_t max;
386 uint32_t sum;
387 uint64_t rsvd4[2];
388 } __attribute__((packed));
389
390 struct iax_raw_completion_record {
391 uint64_t field[8];
392 } __attribute__((packed));
393
394 #endif
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