1 /*
2 * lscpu-arm.c - ARM CPU identification tables
3 *
4 * Copyright (C) 2018 Riku Voipio <riku.voipio@iki.fi>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it would be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * The information here is gathered from
21 * - ARM manuals
22 * - Linux kernel: arch/armX/include/asm/cputype.h
23 * - GCC sources: config/arch/arch-cores.def
24 * - Ancient wisdom
25 * - SMBIOS tables (if applicable)
26 */
27 #include "lscpu.h"
28
29 struct id_part {
30 const int id;
31 const char* name;
32 };
33
34 static const struct id_part arm_part[] = {
35 { 0x810, "ARM810" },
36 { 0x920, "ARM920" },
37 { 0x922, "ARM922" },
38 { 0x926, "ARM926" },
39 { 0x940, "ARM940" },
40 { 0x946, "ARM946" },
41 { 0x966, "ARM966" },
42 { 0xa20, "ARM1020" },
43 { 0xa22, "ARM1022" },
44 { 0xa26, "ARM1026" },
45 { 0xb02, "ARM11 MPCore" },
46 { 0xb36, "ARM1136" },
47 { 0xb56, "ARM1156" },
48 { 0xb76, "ARM1176" },
49 { 0xc05, "Cortex-A5" },
50 { 0xc07, "Cortex-A7" },
51 { 0xc08, "Cortex-A8" },
52 { 0xc09, "Cortex-A9" },
53 { 0xc0d, "Cortex-A17" }, /* Originally A12 */
54 { 0xc0f, "Cortex-A15" },
55 { 0xc0e, "Cortex-A17" },
56 { 0xc14, "Cortex-R4" },
57 { 0xc15, "Cortex-R5" },
58 { 0xc17, "Cortex-R7" },
59 { 0xc18, "Cortex-R8" },
60 { 0xc20, "Cortex-M0" },
61 { 0xc21, "Cortex-M1" },
62 { 0xc23, "Cortex-M3" },
63 { 0xc24, "Cortex-M4" },
64 { 0xc27, "Cortex-M7" },
65 { 0xc60, "Cortex-M0+" },
66 { 0xd01, "Cortex-A32" },
67 { 0xd02, "Cortex-A34" },
68 { 0xd03, "Cortex-A53" },
69 { 0xd04, "Cortex-A35" },
70 { 0xd05, "Cortex-A55" },
71 { 0xd06, "Cortex-A65" },
72 { 0xd07, "Cortex-A57" },
73 { 0xd08, "Cortex-A72" },
74 { 0xd09, "Cortex-A73" },
75 { 0xd0a, "Cortex-A75" },
76 { 0xd0b, "Cortex-A76" },
77 { 0xd0c, "Neoverse-N1" },
78 { 0xd0d, "Cortex-A77" },
79 { 0xd0e, "Cortex-A76AE" },
80 { 0xd13, "Cortex-R52" },
81 { 0xd15, "Cortex-R82" },
82 { 0xd20, "Cortex-M23" },
83 { 0xd21, "Cortex-M33" },
84 { 0xd40, "Neoverse-V1" },
85 { 0xd41, "Cortex-A78" },
86 { 0xd42, "Cortex-A78AE" },
87 { 0xd43, "Cortex-A65AE" },
88 { 0xd44, "Cortex-X1" },
89 { 0xd46, "Cortex-A510" },
90 { 0xd47, "Cortex-A710" },
91 { 0xd48, "Cortex-X2" },
92 { 0xd49, "Neoverse-N2" },
93 { 0xd4a, "Neoverse-E1" },
94 { 0xd4b, "Cortex-A78C" },
95 { 0xd4c, "Cortex-X1C" },
96 { 0xd4d, "Cortex-A715" },
97 { 0xd4e, "Cortex-X3" },
98 { 0xd4f, "Neoverse-V2" },
99 { -1, "unknown" },
100 };
101
102 static const struct id_part brcm_part[] = {
103 { 0x0f, "Brahma-B15" },
104 { 0x100, "Brahma-B53" },
105 { 0x516, "ThunderX2" },
106 { -1, "unknown" },
107 };
108
109 static const struct id_part dec_part[] = {
110 { 0xa10, "SA110" },
111 { 0xa11, "SA1100" },
112 { -1, "unknown" },
113 };
114
115 static const struct id_part cavium_part[] = {
116 { 0x0a0, "ThunderX" },
117 { 0x0a1, "ThunderX-88XX" },
118 { 0x0a2, "ThunderX-81XX" },
119 { 0x0a3, "ThunderX-83XX" },
120 { 0x0af, "ThunderX2-99xx" },
121 { 0x0b0, "OcteonTX2" },
122 { 0x0b1, "OcteonTX2-98XX" },
123 { 0x0b2, "OcteonTX2-96XX" },
124 { 0x0b3, "OcteonTX2-95XX" },
125 { 0x0b4, "OcteonTX2-95XXN" },
126 { 0x0b5, "OcteonTX2-95XXMM" },
127 { 0x0b6, "OcteonTX2-95XXO" },
128 { 0x0b8, "ThunderX3-T110" },
129 { -1, "unknown" },
130 };
131
132 static const struct id_part apm_part[] = {
133 { 0x000, "X-Gene" },
134 { -1, "unknown" },
135 };
136
137 static const struct id_part qcom_part[] = {
138 { 0x00f, "Scorpion" },
139 { 0x02d, "Scorpion" },
140 { 0x04d, "Krait" },
141 { 0x06f, "Krait" },
142 { 0x201, "Kryo" },
143 { 0x205, "Kryo" },
144 { 0x211, "Kryo" },
145 { 0x800, "Falkor-V1/Kryo" },
146 { 0x801, "Kryo-V2" },
147 { 0x802, "Kryo-3XX-Gold" },
148 { 0x803, "Kryo-3XX-Silver" },
149 { 0x804, "Kryo-4XX-Gold" },
150 { 0x805, "Kryo-4XX-Silver" },
151 { 0xc00, "Falkor" },
152 { 0xc01, "Saphira" },
153 { -1, "unknown" },
154 };
155
156 static const struct id_part samsung_part[] = {
157 { 0x001, "exynos-m1" },
158 { 0x002, "exynos-m3" },
159 { 0x003, "exynos-m4" },
160 { 0x004, "exynos-m5" },
161 { -1, "unknown" },
162 };
163
164 static const struct id_part nvidia_part[] = {
165 { 0x000, "Denver" },
166 { 0x003, "Denver 2" },
167 { 0x004, "Carmel" },
168 { -1, "unknown" },
169 };
170
171 static const struct id_part marvell_part[] = {
172 { 0x131, "Feroceon-88FR131" },
173 { 0x581, "PJ4/PJ4b" },
174 { 0x584, "PJ4B-MP" },
175 { -1, "unknown" },
176 };
177
178 static const struct id_part apple_part[] = {
179 { 0x000, "Swift" },
180 { 0x001, "Cyclone" },
181 { 0x002, "Typhoon" },
182 { 0x003, "Typhoon/Capri" },
183 { 0x004, "Twister" },
184 { 0x005, "Twister/Elba/Malta" },
185 { 0x006, "Hurricane" },
186 { 0x007, "Hurricane/Myst" },
187 { 0x008, "Monsoon" },
188 { 0x009, "Mistral" },
189 { 0x00b, "Vortex" },
190 { 0x00c, "Tempest" },
191 { 0x00f, "Tempest-M9" },
192 { 0x010, "Vortex/Aruba" },
193 { 0x011, "Tempest/Aruba" },
194 { 0x012, "Lightning" },
195 { 0x013, "Thunder" },
196 { 0x020, "Icestorm-A14" },
197 { 0x021, "Firestorm-A14" },
198 { 0x022, "Icestorm-M1" },
199 { 0x023, "Firestorm-M1" },
200 { 0x024, "Icestorm-M1-Pro" },
201 { 0x025, "Firestorm-M1-Pro" },
202 { 0x026, "Thunder-M10" },
203 { 0x028, "Icestorm-M1-Max" },
204 { 0x029, "Firestorm-M1-Max" },
205 { 0x030, "Blizzard-A15" },
206 { 0x031, "Avalanche-A15" },
207 { 0x032, "Blizzard-M2" },
208 { 0x033, "Avalanche-M2" },
209 { -1, "unknown" },
210 };
211
212 static const struct id_part faraday_part[] = {
213 { 0x526, "FA526" },
214 { 0x626, "FA626" },
215 { -1, "unknown" },
216 };
217
218 static const struct id_part intel_part[] = {
219 { 0x200, "i80200" },
220 { 0x210, "PXA250A" },
221 { 0x212, "PXA210A" },
222 { 0x242, "i80321-400" },
223 { 0x243, "i80321-600" },
224 { 0x290, "PXA250B/PXA26x" },
225 { 0x292, "PXA210B" },
226 { 0x2c2, "i80321-400-B0" },
227 { 0x2c3, "i80321-600-B0" },
228 { 0x2d0, "PXA250C/PXA255/PXA26x" },
229 { 0x2d2, "PXA210C" },
230 { 0x411, "PXA27x" },
231 { 0x41c, "IPX425-533" },
232 { 0x41d, "IPX425-400" },
233 { 0x41f, "IPX425-266" },
234 { 0x682, "PXA32x" },
235 { 0x683, "PXA930/PXA935" },
236 { 0x688, "PXA30x" },
237 { 0x689, "PXA31x" },
238 { 0xb11, "SA1110" },
239 { 0xc12, "IPX1200" },
240 { -1, "unknown" },
241 };
242
243 static const struct id_part fujitsu_part[] = {
244 { 0x001, "A64FX" },
245 { -1, "unknown" },
246 };
247
248 static const struct id_part hisi_part[] = {
249 { 0xd01, "Kunpeng-920" }, /* aka tsv110 */
250 { 0xd40, "Cortex-A76" }, /* HiSilicon uses this ID though advertises A76 */
251 { -1, "unknown" },
252 };
253
254 static const struct id_part ampere_part[] = {
255 { 0xac3, "Ampere-1" },
256 { 0xac4, "Ampere-1a" },
257 { -1, "unknown" },
258 };
259
260 static const struct id_part ft_part[] = {
261 { 0x660, "FTC660" },
262 { 0x661, "FTC661" },
263 { 0x662, "FTC662" },
264 { 0x663, "FTC663" },
265 { -1, "unknown" },
266 };
267
268 static const struct id_part unknown_part[] = {
269 { -1, "unknown" },
270 };
271
272 struct hw_impl {
273 const int id;
274 const struct id_part *parts;
275 const char *name;
276 };
277
278 static const struct hw_impl hw_implementer[] = {
279 { 0x41, arm_part, "ARM" },
280 { 0x42, brcm_part, "Broadcom" },
281 { 0x43, cavium_part, "Cavium" },
282 { 0x44, dec_part, "DEC" },
283 { 0x46, fujitsu_part, "FUJITSU" },
284 { 0x48, hisi_part, "HiSilicon" },
285 { 0x49, unknown_part, "Infineon" },
286 { 0x4d, unknown_part, "Motorola/Freescale" },
287 { 0x4e, nvidia_part, "NVIDIA" },
288 { 0x50, apm_part, "APM" },
289 { 0x51, qcom_part, "Qualcomm" },
290 { 0x53, samsung_part, "Samsung" },
291 { 0x56, marvell_part, "Marvell" },
292 { 0x61, apple_part, "Apple" },
293 { 0x66, faraday_part, "Faraday" },
294 { 0x69, intel_part, "Intel" },
295 { 0x70, ft_part, "Phytium" },
296 { 0xc0, ampere_part, "Ampere" },
297 { -1, unknown_part, "unknown" },
298 };
299
300 static int parse_id(const char *str)
301 {
302 int id;
303 char *end = NULL;
304
305 if (!str || strncmp(str, "0x",2) != 0)
306 return -EINVAL;
307
308 errno = 0;
309 id = (int) strtol(str, &end, 0);
310 if (errno || str == end)
311 return -EINVAL;
312
313 return id;
314 }
315
316 #define parse_model_id(_cxt) (parse_id((_cxt)->model))
317
318 static inline int parse_implementer_id(struct lscpu_cputype *ct)
319 {
320 if (ct->vendor_id)
321 return ct->vendor_id;
322 ct->vendor_id = parse_id(ct->vendor);
323 return ct->vendor_id;
324 }
325
326 /*
327 * Use model and vendor IDs to decode to human readable names.
328 */
329 static int arm_ids_decode(struct lscpu_cputype *ct)
330 {
331 int impl, part, j;
332 const struct id_part *parts = NULL;
333
334 impl = parse_implementer_id(ct);
335 if (impl <= 0)
336 return -EINVAL; /* no ARM or missing ID */
337
338 /* decode vendor */
339 for (j = 0; hw_implementer[j].id != -1; j++) {
340 if (hw_implementer[j].id == impl) {
341 parts = hw_implementer[j].parts;
342 free(ct->vendor);
343 ct->vendor = xstrdup(hw_implementer[j].name);
344 break;
345 }
346 }
347
348 /* decode model */
349 if (!parts)
350 goto done;
351
352 part = parse_model_id(ct);
353 if (part <= 0)
354 goto done;
355
356 for (j = 0; parts[j].id != -1; j++) {
357 if (parts[j].id == part) {
358 free(ct->modelname);
359 ct->modelname = xstrdup(parts[j].name);
360 break;
361 }
362 }
363 done:
364 return 0;
365 }
366
367 /* use "rXpY" string as stepping */
368 static int arm_rXpY_decode(struct lscpu_cputype *ct)
369 {
370 int impl, revision, variant;
371 char *end = NULL;
372 char buf[8];
373
374 impl = parse_implementer_id(ct);
375
376 if (impl != 0x41 || !ct->revision || !ct->stepping)
377 return -EINVAL;
378
379 errno = 0;
380 revision = (int) strtol(ct->revision, &end, 10);
381 if (errno || ct->revision == end)
382 return -EINVAL;
383
384 errno = 0;
385 variant = (int) strtol(ct->stepping, &end, 0);
386 if (errno || ct->stepping == end)
387 return -EINVAL;
388
389 snprintf(buf, sizeof(buf), "r%dp%d", variant, revision);
390 free(ct->stepping);
391 ct->stepping = xstrdup(buf);
392
393 return 0;
394 }
395
396 static void arm_decode(struct lscpu_cxt *cxt, struct lscpu_cputype *ct)
397 {
398 if (!cxt->noalive && access(_PATH_SYS_DMI, R_OK) == 0)
399 dmi_decode_cputype(ct);
400
401 arm_ids_decode(ct);
402 arm_rXpY_decode(ct);
403
404 if (!cxt->noalive && cxt->is_cluster)
405 ct->nr_socket_on_cluster = get_number_of_physical_sockets_from_dmi();
406 }
407
408 static int is_cluster_arm(struct lscpu_cxt *cxt)
409 {
410 struct stat st;
411
412 if (!cxt->noalive
413 && strcmp(cxt->arch->name, "aarch64") == 0
414 && stat(_PATH_ACPI_PPTT, &st) < 0 && cxt->ncputypes == 1)
415 return 1;
416 else
417 return 0;
418 }
419
420 void lscpu_decode_arm(struct lscpu_cxt *cxt)
421 {
422 size_t i;
423
424 cxt->is_cluster = is_cluster_arm(cxt);
425
426 for (i = 0; i < cxt->ncputypes; i++)
427 arm_decode(cxt, cxt->cputypes[i]);
428 }