1 /* Copyright (C) 1999-2023 Free Software Foundation, Inc.
2 This file is part of the GNU C Library.
3
4 The GNU C Library is free software; you can redistribute it and/or
5 modify it under the terms of the GNU Lesser General Public
6 License as published by the Free Software Foundation; either
7 version 2.1 of the License, or (at your option) any later version.
8
9 The GNU C Library is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 Lesser General Public License for more details.
13
14 You should have received a copy of the GNU Lesser General Public
15 License along with the GNU C Library; if not, see
16 <https://www.gnu.org/licenses/>. */
17
18 /*
19 * Powerpc Feature masks for the Aux Vector Hardware Capabilities (AT_HWCAP).
20 * This entry is copied to _dl_hwcap or rtld_global._dl_hwcap during startup.
21 */
22 #define _SYSDEPS_SYSDEP_H 1
23 #include <bits/hwcap.h>
24
25 #define PPC_FEATURE_970 (PPC_FEATURE_POWER4 + PPC_FEATURE_HAS_ALTIVEC)
26
27 #ifdef __ASSEMBLER__
28
29 /* Symbolic names for the registers. The only portable way to write asm
30 code is to use number but this produces really unreadable code.
31 Therefore these symbolic names. */
32
33 /* Integer registers. */
34 #define r0 0
35 #define r1 1
36 #define r2 2
37 #define r3 3
38 #define r4 4
39 #define r5 5
40 #define r6 6
41 #define r7 7
42 #define r8 8
43 #define r9 9
44 #define r10 10
45 #define r11 11
46 #define r12 12
47 #define r13 13
48 #define r14 14
49 #define r15 15
50 #define r16 16
51 #define r17 17
52 #define r18 18
53 #define r19 19
54 #define r20 20
55 #define r21 21
56 #define r22 22
57 #define r23 23
58 #define r24 24
59 #define r25 25
60 #define r26 26
61 #define r27 27
62 #define r28 28
63 #define r29 29
64 #define r30 30
65 #define r31 31
66
67 /* Floating-point registers. */
68 #define fp0 0
69 #define fp1 1
70 #define fp2 2
71 #define fp3 3
72 #define fp4 4
73 #define fp5 5
74 #define fp6 6
75 #define fp7 7
76 #define fp8 8
77 #define fp9 9
78 #define fp10 10
79 #define fp11 11
80 #define fp12 12
81 #define fp13 13
82 #define fp14 14
83 #define fp15 15
84 #define fp16 16
85 #define fp17 17
86 #define fp18 18
87 #define fp19 19
88 #define fp20 20
89 #define fp21 21
90 #define fp22 22
91 #define fp23 23
92 #define fp24 24
93 #define fp25 25
94 #define fp26 26
95 #define fp27 27
96 #define fp28 28
97 #define fp29 29
98 #define fp30 30
99 #define fp31 31
100
101 /* Condition code registers. */
102 #define cr0 0
103 #define cr1 1
104 #define cr2 2
105 #define cr3 3
106 #define cr4 4
107 #define cr5 5
108 #define cr6 6
109 #define cr7 7
110
111 /* Vector registers. */
112 #define v0 0
113 #define v1 1
114 #define v2 2
115 #define v3 3
116 #define v4 4
117 #define v5 5
118 #define v6 6
119 #define v7 7
120 #define v8 8
121 #define v9 9
122 #define v10 10
123 #define v11 11
124 #define v12 12
125 #define v13 13
126 #define v14 14
127 #define v15 15
128 #define v16 16
129 #define v17 17
130 #define v18 18
131 #define v19 19
132 #define v20 20
133 #define v21 21
134 #define v22 22
135 #define v23 23
136 #define v24 24
137 #define v25 25
138 #define v26 26
139 #define v27 27
140 #define v28 28
141 #define v29 29
142 #define v30 30
143 #define v31 31
144
145 #define VRSAVE 256
146
147 /* The 32-bit words of a 64-bit dword are at these offsets in memory. */
148 #if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN
149 # define LOWORD 0
150 # define HIWORD 4
151 #else
152 # define LOWORD 4
153 # define HIWORD 0
154 #endif
155
156 /* The high 16-bit word of a 64-bit dword is at this offset in memory. */
157 #if defined __LITTLE_ENDIAN__ || defined _LITTLE_ENDIAN
158 # define HISHORT 6
159 #else
160 # define HISHORT 0
161 #endif
162
163 /* This seems to always be the case on PPC. */
164 #define ALIGNARG(log2) log2
165 #define ASM_SIZE_DIRECTIVE(name) .size name,.-name
166
167 #endif /* __ASSEMBLER__ */