1 /* FPU control word bits. Mips version.
2 Copyright (C) 1996-2023 Free Software Foundation, Inc.
3 This file is part of the GNU C Library.
4
5 The GNU C Library is free software; you can redistribute it and/or
6 modify it under the terms of the GNU Lesser General Public
7 License as published by the Free Software Foundation; either
8 version 2.1 of the License, or (at your option) any later version.
9
10 The GNU C Library is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 Lesser General Public License for more details.
14
15 You should have received a copy of the GNU Lesser General Public
16 License along with the GNU C Library. If not, see
17 <https://www.gnu.org/licenses/>. */
18
19 #ifndef _FPU_CONTROL_H
20 #define _FPU_CONTROL_H
21
22 /* MIPS FPU floating point control register bits.
23 *
24 * 31-25 -> floating point conditions code bits 7-1. These bits are only
25 * available in MIPS IV.
26 * 24 -> flush denormalized results to zero instead of
27 * causing unimplemented operation exception. This bit is only
28 * available for MIPS III and newer.
29 * 23 -> Condition bit
30 * 22-21 -> reserved for architecture implementers
31 * 20 -> reserved (read as 0, write with 0)
32 * 19 -> IEEE 754-2008 non-arithmetic ABS.fmt and NEG.fmt enable
33 * 18 -> IEEE 754-2008 recommended NaN encoding enable
34 * 17 -> cause bit for unimplemented operation
35 * 16 -> cause bit for invalid exception
36 * 15 -> cause bit for division by zero exception
37 * 14 -> cause bit for overflow exception
38 * 13 -> cause bit for underflow exception
39 * 12 -> cause bit for inexact exception
40 * 11 -> enable exception for invalid exception
41 * 10 -> enable exception for division by zero exception
42 * 9 -> enable exception for overflow exception
43 * 8 -> enable exception for underflow exception
44 * 7 -> enable exception for inexact exception
45 * 6 -> flag invalid exception
46 * 5 -> flag division by zero exception
47 * 4 -> flag overflow exception
48 * 3 -> flag underflow exception
49 * 2 -> flag inexact exception
50 * 1-0 -> rounding control
51 *
52 *
53 * Rounding Control:
54 * 00 - rounding to nearest (RN)
55 * 01 - rounding toward zero (RZ)
56 * 10 - rounding (up) toward plus infinity (RP)
57 * 11 - rounding (down)toward minus infinity (RM)
58 */
59
60 #include <features.h>
61
62 #ifdef __mips_soft_float
63
64 #define _FPU_RESERVED 0xffffffff
65 #define _FPU_DEFAULT 0x00000000
66 typedef unsigned int fpu_control_t;
67 #define _FPU_GETCW(cw) (cw) = 0
68 #define _FPU_SETCW(cw) (void) (cw)
69 extern fpu_control_t __fpu_control;
70
71 #else /* __mips_soft_float */
72
73 /* Masks for interrupts. */
74 #define _FPU_MASK_V 0x0800 /* Invalid operation */
75 #define _FPU_MASK_Z 0x0400 /* Division by zero */
76 #define _FPU_MASK_O 0x0200 /* Overflow */
77 #define _FPU_MASK_U 0x0100 /* Underflow */
78 #define _FPU_MASK_I 0x0080 /* Inexact operation */
79
80 /* Flush denormalized numbers to zero. */
81 #define _FPU_FLUSH_TZ 0x1000000
82
83 /* IEEE 754-2008 compliance control. */
84 #define _FPU_ABS2008 0x80000
85 #define _FPU_NAN2008 0x40000
86
87 /* Rounding control. */
88 #define _FPU_RC_NEAREST 0x0 /* RECOMMENDED */
89 #define _FPU_RC_ZERO 0x1
90 #define _FPU_RC_UP 0x2
91 #define _FPU_RC_DOWN 0x3
92 /* Mask for rounding control. */
93 #define _FPU_RC_MASK 0x3
94
95 #define _FPU_RESERVED 0xfe8c0000 /* Reserved bits in cw, incl ABS/NAN2008. */
96
97
98 /* The fdlibm code requires strict IEEE double precision arithmetic,
99 and no interrupts for exceptions, rounding to nearest. */
100 #ifdef __mips_nan2008
101 # define _FPU_DEFAULT 0x000C0000
102 #else
103 # define _FPU_DEFAULT 0x00000000
104 #endif
105
106 /* IEEE: same as above, but exceptions. */
107 #ifdef __mips_nan2008
108 # define _FPU_IEEE 0x000C0F80
109 #else
110 # define _FPU_IEEE 0x00000F80
111 #endif
112
113 /* Type of the control word. */
114 typedef unsigned int fpu_control_t __attribute__ ((__mode__ (__SI__)));
115
116 /* Macros for accessing the hardware control word. */
117 extern fpu_control_t __mips_fpu_getcw (void) __THROW;
118 extern void __mips_fpu_setcw (fpu_control_t) __THROW;
119 #ifdef __mips16
120 # define _FPU_GETCW(cw) do { (cw) = __mips_fpu_getcw (); } while (0)
121 # define _FPU_SETCW(cw) __mips_fpu_setcw (cw)
122 #else
123 # define _FPU_GETCW(cw) __asm__ volatile ("cfc1 %0,$31" : "=r" (cw))
124 # define _FPU_SETCW(cw) __asm__ volatile ("ctc1 %0,$31" : : "r" (cw))
125 #endif
126
127 /* Default control word set at startup. */
128 extern fpu_control_t __fpu_control;
129
130 #endif /* __mips_soft_float */
131
132 #endif /* fpu_control.h */