1  /* Copyright (C) 2008-2023 Free Software Foundation, Inc.
       2     Contributed by Richard Henderson <rth@redhat.com>.
       3  
       4     This file is part of the GNU Transactional Memory Library (libitm).
       5  
       6     Libitm is free software; you can redistribute it and/or modify it
       7     under the terms of the GNU General Public License as published by
       8     the Free Software Foundation; either version 3 of the License, or
       9     (at your option) any later version.
      10  
      11     Libitm is distributed in the hope that it will be useful, but WITHOUT ANY
      12     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
      13     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
      14     more details.
      15  
      16     Under Section 7 of GPL version 3, you are granted additional
      17     permissions described in the GCC Runtime Library Exception, version
      18     3.1, as published by the Free Software Foundation.
      19  
      20     You should have received a copy of the GNU General Public License and
      21     a copy of the GCC Runtime Library Exception along with this program;
      22     see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
      23     <http://www.gnu.org/licenses/>.  */
      24  
      25  // We'll be using some of the cpu builtins, and their associated types.
      26  #include <x86intrin.h>
      27  #include <cpuid.h>
      28  
      29  namespace GTM HIDDEN {
      30  
      31  /* ??? This doesn't work for Win64.  */
      32  typedef struct gtm_jmpbuf
      33  {
      34    void *cfa;
      35  #ifdef __x86_64__
      36    unsigned long long rbx;
      37    unsigned long long rbp;
      38    unsigned long long r12;
      39    unsigned long long r13;
      40    unsigned long long r14;
      41    unsigned long long r15;
      42    unsigned long long ssp;
      43    unsigned long long rip;
      44  #else
      45    unsigned long ebx;
      46    unsigned long esi;
      47    unsigned long edi;
      48    unsigned long ebp;
      49    unsigned long ssp;
      50    unsigned long eip;
      51  #endif
      52  } gtm_jmpbuf;
      53  
      54  /* x86 doesn't require strict alignment for the basic types.  */
      55  #define STRICT_ALIGNMENT 0
      56  
      57  /* The size of one line in hardware caches (in bytes). */
      58  #define HW_CACHELINE_SIZE 64
      59  
      60  
      61  static inline void
      62  cpu_relax (void)
      63  {
      64    __builtin_ia32_pause ();
      65  }
      66  
      67  // Use Intel RTM if supported by the assembler.
      68  // See gtm_thread::begin_transaction for how these functions are used.
      69  #ifdef HAVE_AS_RTM
      70  #define USE_HTM_FASTPATH
      71  #ifdef __x86_64__
      72  // Use the custom fastpath in ITM_beginTransaction.
      73  #define HTM_CUSTOM_FASTPATH
      74  #endif
      75  
      76  static inline bool
      77  htm_available ()
      78  {
      79    const unsigned cpuid_rtm = bit_RTM;
      80    unsigned vendor;
      81  
      82    if (__get_cpuid_max (0, &vendor) >= 7)
      83      {
      84        unsigned a, b, c, d;
      85        unsigned family;
      86  
      87        __cpuid (1, a, b, c, d);
      88        family = (a >> 8) & 0x0f;
      89        /* TSX is broken on some processors.  TSX can be disabled by microcode,
      90  	 but we cannot reliably detect whether the microcode has been
      91  	 updated.  Therefore, do not report availability of TSX on these
      92  	 processors.  We use the same approach here as in glibc (see
      93  	 https://sourceware.org/ml/libc-alpha/2016-12/msg00470.html).  */
      94        if (vendor == signature_INTEL_ebx && family == 0x06)
      95  	{
      96  	  unsigned model = ((a >> 4) & 0x0f) + ((a >> 12) & 0xf0);
      97  	  unsigned stepping = a & 0x0f;
      98  	  if (model == 0x3c
      99  	      /* Xeon E7 v3 has correct TSX if stepping >= 4.  */
     100  	      || (model == 0x3f && stepping < 4)
     101  	      || model == 0x45
     102  	      || model == 0x46)
     103  	    return false;
     104  	}
     105  
     106        __cpuid_count (7, 0, a, b, c, d);
     107        if (b & cpuid_rtm)
     108  	return true;
     109      }
     110    return false;
     111  }
     112  
     113  static inline uint32_t
     114  htm_init ()
     115  {
     116    // Maximum number of times we try to execute a transaction as a HW
     117    // transaction.
     118    // ??? Why 2?  Any offline or runtime tuning necessary?
     119    return htm_available () ? 2 : 0;
     120  }
     121  
     122  static inline uint32_t
     123  htm_begin ()
     124  {
     125    return _xbegin();
     126  }
     127  
     128  static inline bool
     129  htm_begin_success (uint32_t begin_ret)
     130  {
     131    return begin_ret == _XBEGIN_STARTED;
     132  }
     133  
     134  static inline void
     135  htm_commit ()
     136  {
     137    _xend();
     138  }
     139  
     140  static inline void
     141  htm_abort ()
     142  {
     143    // ??? According to a yet unpublished ABI rule, 0xff is reserved and
     144    // supposed to signal a busy lock.  Source: andi.kleen@intel.com
     145    _xabort(0xff);
     146  }
     147  
     148  static inline bool
     149  htm_abort_should_retry (uint32_t begin_ret)
     150  {
     151    return begin_ret & _XABORT_RETRY;
     152  }
     153  
     154  /* Returns true iff a hardware transaction is currently being executed.  */
     155  static inline bool
     156  htm_transaction_active ()
     157  {
     158    return _xtest() != 0;
     159  }
     160  #endif
     161  
     162  
     163  } // namespace GTM