1  /* { dg-do compile } */
       2  /* { dg-options "-fdump-rtl-cmpelim -dp" } */
       3  /* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */
       4  
       5  typedef unsigned int __attribute__ ((mode (SI))) ulong_t;
       6  typedef int __attribute__ ((mode (SI))) long_t;
       7  typedef int __attribute__ ((mode (QI))) int_t;
       8  
       9  ulong_t
      10  eq_rotlsi (ulong_t x, int_t y)
      11  {
      12    long_t v;
      13  
      14    v = x << y | x >> 8 * sizeof (x) - y;
      15    if (v == 0)
      16      return v;
      17    else
      18      return v + 2;
      19  }
      20  
      21  /* Expect assembly like:
      22  
      23  	rotl 8(%ap),4(%ap),%r0		# 36	[c=40]  *rotlsi3_ccz
      24  	jeql .L1			# 38	[c=26]  *branch_ccz
      25  	addl2 $2,%r0			# 35	[c=32]  *addsi3
      26  .L1:
      27  
      28   */
      29  
      30  /* { dg-final { scan-rtl-dump-times "deleting insn with uid" 1 "cmpelim" } } */
      31  /* { dg-final { scan-assembler-not "\t(bit|cmpz?|tst). " } } */
      32  /* { dg-final { scan-assembler "rotlsi\[^ \]*_ccz(/\[0-9\]+)?\n" } } */
      33  /* { dg-final { scan-assembler "branch_ccz\n" } } */