1  /* Check that the XF registers are not clobbered by an integer division
       2     that is done using double precision FPU division.  */
       3  
       4  /* { dg-do run { target { default_single_fpu && has_xf_regs } } } */
       5  /* { dg-options "-O1 -mdiv=call-fp" }  */
       6  
       7  #include <assert.h>
       8  #include <stdlib.h>
       9  
      10  extern void __set_fpscr (int);
      11  
      12  void
      13  write_xf0 (float* f)
      14  {
      15    __asm__ __volatile__ ("frchg; fmov.s @%0,fr0; frchg" : : "r" (f) : "memory");
      16  }
      17   
      18  void
      19  read_xf0 (float* f)
      20  {
      21    __asm__ __volatile__ ("frchg; fmov.s fr0,@%0; frchg" : : "r" (f) : "memory");
      22  }
      23  
      24  int __attribute__ ((noinline))
      25  test_00 (int a, int b)
      26  {
      27    return a / b;
      28  }
      29  
      30  unsigned int __attribute__ ((noinline))
      31  test_01 (unsigned a, unsigned b)
      32  {
      33    return a / b;
      34  }
      35  
      36  int __attribute__ ((noinline))
      37  test_02 (int x)
      38  {
      39    return x & 0;
      40  }
      41  
      42  int
      43  main (void)
      44  {
      45    float test_value;
      46    int r = 0;
      47  
      48    /* Set FPSCR.FR to 1.  */
      49    __set_fpscr (0x200000);
      50  
      51    test_value = 123;
      52    write_xf0 (&test_value);
      53    r += test_00 (40, 4);
      54    read_xf0 (&test_value);
      55    assert (test_value == 123);
      56  
      57    test_value = 321;
      58    write_xf0 (&test_value);
      59    r += test_01 (50, 5);
      60    read_xf0 (&test_value);
      61    assert (test_value == 321);
      62  
      63    return test_02 (r);
      64  }