1  /* Tests to check the utilization of addc, subc and negc instructions in
       2     special cases.  If everything works as expected we won't see any
       3     movt instructions in these cases.  */
       4  /* { dg-do compile }  */
       5  /* { dg-options "-O2" } */
       6  
       7  /* { dg-final { scan-assembler-times "addc" 6 } } */
       8  /* { dg-final { scan-assembler-times "subc" 4 } } */
       9  /* { dg-final { scan-assembler-times "sett" 5 } } */
      10  
      11  /* { dg-final { scan-assembler-times "negc" 2 { target { ! sh2a } } } }  */
      12  /* { dg-final { scan-assembler-not "movt" { target { ! sh2a } } } }  */
      13  
      14  /* { dg-final { scan-assembler-times "bld" 1 { target { sh2a } } } }  */
      15  /* { dg-final { scan-assembler-times "movt" 1 { target { sh2a } } } }  */
      16  
      17  int
      18  test_00 (int a, int b, int c, int d)
      19  {
      20    /* 1x addc, 1x sett  */
      21    return a + b + 1;
      22  }
      23  
      24  int
      25  test_01 (int a, int b, int c, int d)
      26  {
      27    /* 1x addc  */
      28    return a + (c == d);
      29  }
      30  
      31  int
      32  test_02 (int a, int b, int c, int d)
      33  {
      34    /* 1x subc, 1x sett  */
      35    return a - b - 1;
      36  }
      37  
      38  int
      39  test_03 (int a, int b, int c, int d)
      40  {
      41    /* 1x subc  */
      42    return a - (c == d);
      43  }
      44  
      45  int
      46  test_04 (int a, int b, int c, int d)
      47  {
      48    /* 1x addc, 1x sett  */
      49    return a + b + c + 1;
      50  }
      51  
      52  int
      53  test_05 (int a, int b, int c, int d)
      54  {
      55    /* 1x subc, 1x sett  */
      56    return a - b - c - 1;
      57  }
      58  
      59  int
      60  test_06 (int a, int b, int c, int d)
      61  {
      62    /* 1x negc  */
      63    return 0 - a - (b == c);
      64  }
      65  
      66  int
      67  test_07 (int *vec)
      68  {
      69    /* Must not see a 'sett' or 'addc' here.
      70       This is a case where combine tries to produce
      71       'a + (0 - b) + 1' out of 'a - b + 1'.
      72       On non-SH2A there is a 'tst + negc', on SH2A a 'bld + movt'.  */
      73    int z = vec[0];
      74    int vi = vec[1];
      75    int zi = vec[2];
      76  
      77    if (zi != 0 && z < -1)
      78      vi -= (((vi >> 7) & 0x01) << 1) - 1;
      79  
      80    return vi;
      81  }
      82  
      83  int
      84  test_08 (int a)
      85  {
      86    /* 1x addc, 1x sett  */
      87    return (a << 1) + 1;
      88  }
      89  
      90  unsigned int
      91  test_09 (unsigned int x)
      92  {
      93    /* 1x tst, 1x addc  */
      94    return x - (x != 0);
      95  }
      96  
      97  unsigned int
      98  test_10 (unsigned int x)
      99  {
     100    /* 1x tst, 1x subc  */
     101    return x + (x == 0);
     102  }
     103  
     104  unsigned int
     105  test_11 (unsigned int x)
     106  {
     107    /* 1x tst, 1x addc  */
     108    return x + (x != 0);
     109  }
     110