1  /* Check that we use the scalar variants of vector compares.  */
       2  
       3  /* { dg-do compile { target { s390*-*-* } } } */
       4  /* { dg-options "-O3 -mzarch -march=z13 -fno-asynchronous-unwind-tables" } */
       5  
       6  int
       7  eq (double a, double b)
       8  {
       9    asm ("" : : :
      10         "f0", "f1",  "f2",  "f3",  "f4" , "f5",  "f6",  "f7",
      11         "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
      12    return a == b;
      13  }
      14  
      15  /* { dg-final { scan-assembler "eq:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochie\t%r2,1" { target { ! lp64 } } } } */
      16  /* { dg-final { scan-assembler "eq:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghie\t%r2,1" { target lp64 } } } */
      17  
      18  int
      19  ne (double a, double b)
      20  {
      21    asm ("" : : :
      22         "f0", "f1",  "f2",  "f3",  "f4" , "f5",  "f6",  "f7",
      23         "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
      24    return a != b;
      25  }
      26  
      27  /* { dg-final { scan-assembler "ne:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochine\t%r2,1" { target { ! lp64 } } } } */
      28  /* { dg-final { scan-assembler "ne:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghine\t%r2,1" { target lp64 } } } */
      29  
      30  int
      31  gt (double a, double b)
      32  {
      33    asm ("" : : :
      34         "f0", "f1",  "f2",  "f3",  "f4" , "f5",  "f6",  "f7",
      35         "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
      36    return a > b;
      37  }
      38  
      39  /* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochih\t%r2,1" { target { ! lp64 } } } } */
      40  /* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghih\t%r2,1" { target lp64 } } } */
      41  
      42  int
      43  ge (double a, double b)
      44  {
      45    asm ("" : : :
      46         "f0", "f1",  "f2",  "f3",  "f4" , "f5",  "f6",  "f7",
      47         "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
      48    return a >= b;
      49  }
      50  
      51  /* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochihe\t%r2,1" { target { ! lp64 } } } } */
      52  /* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghihe\t%r2,1" { target lp64 } } } */
      53  
      54  int
      55  lt (double a, double b)
      56  {
      57    asm ("" : : :
      58         "f0", "f1",  "f2",  "f3",  "f4" , "f5",  "f6",  "f7",
      59         "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
      60    return a < b;
      61  }
      62  
      63  /* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochil\t%r2,1" { target { ! lp64 } } } } */
      64  /* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghil\t%r2,1" { target lp64 } } } */
      65  
      66  int
      67  le (double a, double b)
      68  {
      69    asm ("" : : :
      70         "f0", "f1",  "f2",  "f3",  "f4" , "f5",  "f6",  "f7",
      71         "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15");
      72    return a <= b;
      73  }
      74  
      75  /* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochile\t%r2,1" { target { ! lp64 } } } } */
      76  /* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlocghile\t%r2,1" { target lp64 } } } */