(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
riscv/
shorten-memrefs-2.c
       1  /* { dg-options "-march=rv32imc -mabi=ilp32" } */
       2  /* { dg-skip-if "" { *-*-* } { "*" } { "-Os" } } */
       3  
       4  /* shorten_memrefs should rewrite these load/stores into a compressible
       5     format.  */
       6  
       7  void
       8  store1a (int *array, int a)
       9  {
      10    array[200] = a;
      11    array[201] = a;
      12    array[202] = a;
      13    array[203] = a;
      14  }
      15  
      16  void
      17  store2a (long long *array, long long a)
      18  {
      19    array[200] = a;
      20    array[201] = a;
      21    array[202] = a;
      22    array[203] = a;
      23  }
      24  
      25  int
      26  load1r (int *array)
      27  {
      28    int a = 0;
      29    a += array[200];
      30    a += array[201];
      31    a += array[202];
      32    a += array[203];
      33    return a;
      34  }
      35  
      36  long long
      37  load2r (long long *array)
      38  {
      39    int a = 0;
      40    a += array[200];
      41    a += array[201];
      42    a += array[202];
      43    a += array[203];
      44    return a;
      45  }
      46  
      47  /* { dg-final { scan-assembler "store1a:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
      48  /* The sd insns in store2a are not rewritten because shorten_memrefs currently
      49     only optimizes lw and sw.
      50  /* { dg-final { scan-assembler "store2a:\n(\t?\\.\[^\n\]*\n)*\taddi" { xfail riscv*-*-*  } } } */
      51  /* { dg-final { scan-assembler "load1r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */
      52  /* { dg-final { scan-assembler "load2r:\n(\t?\\.\[^\n\]*\n)*\taddi" } } */