1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
       7    size_t avl = __riscv_vsetvlmax_e8mf8();
       8  
       9    for (size_t i = 0; i < m; i++) {
      10      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
      11      v0 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 100, avl);
      12      __riscv_vse8_v_i8mf8(out + i, v0, avl);
      13    }
      14  }
      15  
      16  /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      17  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      18  /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */