1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f(int8_t *base, int8_t *out, size_t vl, size_t m, size_t n) {
       7    vint8mf4_t v1 = *(vint8mf4_t*) (base + 100000);
       8    size_t avl = __riscv_vsetvl_e8mf8(vl);
       9    for (size_t i = 0; i < m; i++) {
      10      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
      11      if (n > 100) {
      12        __riscv_vse8_v_i8mf4(out + i, v1, avl);
      13      } else {
      14        __riscv_vse8_v_i8mf8(out + i, v0, avl);
      15      }
      16    }
      17  }
      18  
      19  /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      20  /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */