1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f(int8_t *base, int8_t *out, size_t vl, size_t m) {
       7    size_t avl;
       8    if (m > 100)
       9      avl = __riscv_vsetvl_e8mf8(vl << 10);
      10    else
      11      avl = __riscv_vsetvl_e8mf8(vl);
      12  
      13    for (size_t i = 0; i < m; i++) {
      14      vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i, avl);
      15      __riscv_vse8_v_i8mf8(out + i, v0, avl);
      16    }
      17  }
      18  
      19  /* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      20  /* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*10} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */