1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (void * restrict in, void * restrict out, void * restrict in2, void * restrict out2,  int n, int cond)
       7  {
       8    if (cond == 0) {
       9      vint8mf8_t v = *(vint8mf8_t*)(in + 100);
      10      *(vint8mf8_t*)(out + 100) = v;
      11      for (int i = 0; i < n; i++)
      12        {
      13          vint16mf4_t v2;
      14          *(vint16mf4_t*)(out + i + 100) = v2;
      15        }
      16    } else {
      17      vuint8mf8_t v;
      18      *(vuint8mf8_t*)(out + 1000) = v;
      19      for (int i = 0; i < n; i++)
      20        {
      21          vfloat32mf2_t v2;
      22          *(vfloat32mf2_t*)(out + i + 1000) = v2;
      23          vbool64_t v3;
      24          *(vbool64_t*)(out + i + 2000) = v3;
      25          vbool32_t v4;
      26          *(vbool32_t*)(out + i + 3000) = v4;
      27          vbool16_t v5;
      28          *(vbool16_t*)(out + i + 4000) = v5;
      29          vbool8_t v6;
      30          *(vbool8_t*)(out + i + 5000) = v6;
      31          vbool4_t v7;
      32          *(vbool4_t*)(out + i + 6000) = v7;
      33          vbool2_t v8;
      34          *(vbool2_t*)(out + i + 7000) = v8;
      35          vbool1_t v9;
      36          *(vbool1_t*)(out + i + 8000) = v9;
      37          vuint32mf2_t v10;
      38          *(vuint32mf2_t*)(out + i + 100000) = v10;
      39        }
      40    }
      41  }
      42  
      43  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      44  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      45  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      46  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      47  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      48  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      49  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      50  
      51  /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      52  /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      53  /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */
      54  /* { dg-final { scan-assembler-times {vsetvli} 11 { target { no-opts "-O0"  no-opts "-O1"  no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts "-g" } } } } */