1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void fn3 (void);
       7  
       8  void f (void * restrict in, void * restrict out, int n)
       9  {
      10    vint8mf8_t v1 = __riscv_vle8_v_i8mf8 (in + 1, 5);
      11    vint16mf4_t v2 = __riscv_vle16_v_i16mf4 (in + 2, 5);
      12    vint32mf2_t v3 = __riscv_vle32_v_i32mf2 (in + 3, 5);
      13    vfloat32mf2_t v4 = __riscv_vle32_v_f32mf2 (in + 4, 5);
      14    
      15    __riscv_vse8_v_i8mf8 (out + 1, v1, 5);
      16    __riscv_vse16_v_i16mf4 (out + 2, v2, 5);
      17    __riscv_vse32_v_i32mf2 (out + 3, v3, 5);
      18    __riscv_vse32_v_f32mf2 (out + 4, v4, 5);
      19  
      20    for (int i = 0; i < n; i++)
      21      {
      22        vint16mf4_t v = __riscv_vle16_v_i16mf4 (in + i + 5, 7);
      23        __riscv_vse16_v_i16mf4 (out + i + 5, v, 7);
      24        fn3 ();
      25      }
      26  }
      27  
      28  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      29  /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vsetivli\s+zero,\s*7,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */