1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  
       7  void f8 (void * restrict in, void * restrict out, int l, int n, int m)
       8  {
       9    for (int i = 0; i < l; i++){
      10      for (int j = 0; j < m; j++){
      11        for (int k = 0; k < n; k++)
      12          {
      13            vfloat64m1_t v = __riscv_vle64_v_f64m1 (in + i + j, 17);
      14            __riscv_vse64_v_f64m1 (out + i + j, v, 17);
      15          }
      16      }
      17    }
      18  }
      19  
      20  void f9 (void * restrict in, void * restrict out, int l, int n, int m)
      21  {
      22    for (int i = 0; i < l; i++){
      23      for (int j = 0; j < m; j++){
      24        for (int k = 0; k < n; k++)
      25          {
      26            vfloat64m2_t v = __riscv_vle64_v_f64m2 (in + i + j, 17);
      27            __riscv_vse64_v_f64m2 (out + i + j, v, 17);
      28          }
      29      }
      30    }
      31  }
      32  
      33  void f11 (void * restrict in, void * restrict out, int l, int n, int m)
      34  {
      35    for (int i = 0; i < l; i++){
      36      for (int j = 0; j < m; j++){
      37        for (int k = 0; k < n; k++)
      38          {
      39            vfloat64m4_t v = __riscv_vle64_v_f64m4 (in + i + j, 17);
      40            __riscv_vse64_v_f64m4 (out + i + j, v, 17);
      41          }
      42      }
      43    }
      44  }
      45  
      46  void f13 (void * restrict in, void * restrict out, int l, int n, int m)
      47  {
      48    for (int i = 0; i < l; i++){
      49      for (int j = 0; j < m; j++){
      50        for (int k = 0; k < n; k++)
      51          {
      52            vfloat64m8_t v = __riscv_vle64_v_f64m8 (in + i + j, 17);
      53            __riscv_vse64_v_f64m8 (out + i + j, v, 17);
      54          }
      55      }
      56    }
      57  }
      58  
      59  
      60  /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle64\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 4 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      61  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      62  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      63  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      64  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e64,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */