1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f5 (void * restrict in, void * restrict out, int l, int n, int m)
       7  {
       8    for (int i = 0; i < l; i++){
       9      for (int j = 0; j < m; j++){
      10        for (int k = 0; k < n; k++)
      11          {
      12            vfloat32mf2_t v = __riscv_vle32_v_f32mf2 (in + i + j, 17);
      13            __riscv_vse32_v_f32mf2 (out + i + j, v, 17);
      14          }
      15      }
      16    }
      17  }
      18  
      19  void f7 (void * restrict in, void * restrict out, int l, int n, int m)
      20  {
      21    for (int i = 0; i < l; i++){
      22      for (int j = 0; j < m; j++){
      23        for (int k = 0; k < n; k++)
      24          {
      25            vfloat32m1_t v = __riscv_vle32_v_f32m1 (in + i + j, 17);
      26            __riscv_vse32_v_f32m1 (out + i + j, v, 17);
      27          }
      28      }
      29    }
      30  }
      31  
      32  void f9 (void * restrict in, void * restrict out, int l, int n, int m)
      33  {
      34    for (int i = 0; i < l; i++){
      35      for (int j = 0; j < m; j++){
      36        for (int k = 0; k < n; k++)
      37          {
      38            vfloat32m2_t v = __riscv_vle32_v_f32m2 (in + i + j, 17);
      39            __riscv_vse32_v_f32m2 (out + i + j, v, 17);
      40          }
      41      }
      42    }
      43  }
      44  
      45  void f11 (void * restrict in, void * restrict out, int l, int n, int m)
      46  {
      47    for (int i = 0; i < l; i++){
      48      for (int j = 0; j < m; j++){
      49        for (int k = 0; k < n; k++)
      50          {
      51            vfloat32m4_t v = __riscv_vle32_v_f32m4 (in + i + j, 17);
      52            __riscv_vse32_v_f32m4 (out + i + j, v, 17);
      53          }
      54      }
      55    }
      56  }
      57  
      58  void f13 (void * restrict in, void * restrict out, int l, int n, int m)
      59  {
      60    for (int i = 0; i < l; i++){
      61      for (int j = 0; j < m; j++){
      62        for (int k = 0; k < n; k++)
      63          {
      64            vfloat32m8_t v = __riscv_vle32_v_f32m8 (in + i + j, 17);
      65            __riscv_vse32_v_f32m8 (out + i + j, v, 17);
      66          }
      67      }
      68    }
      69  }
      70  
      71  
      72  /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle32\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 5 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      73  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      74  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m1,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      75  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m2,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      76  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      77  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*17,\s*e32,\s*m8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */