(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
riscv/
rvv/
vsetvl/
imm_conflict-5.c
       1  #include "riscv_vector.h"
       2  
       3  /* { dg-do compile } */
       4  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
       5  
       6  #include "riscv_vector.h"
       7  
       8  void f (void * restrict in, void * restrict out, int n, int cond)
       9  {
      10    if (n > cond) {
      11      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 600, 5);
      12      vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + 600, 5);
      13      __riscv_vse8_v_i8mf8 (out + 600, v2, 5);
      14    } else {
      15      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + 700, 5);
      16      __riscv_vse8_v_i8mf8 (out + 700, v, 5);
      17    }
      18  
      19    for (int i = 0 ; i < n * n * n * n; i++) {
      20      vint8mf8_t v = *(vint8mf8_t*) (in + 900 + i);
      21      *(vint8mf8_t*) (out + 900 + i) = v;
      22    }
      23  
      24    for (int i = 0 ; i < n; i++) {
      25      vint32m1_t v = __riscv_vle32_v_i32m1 (in + 1000 + i, 19);
      26      __riscv_vse32_v_i32m1 (out + 1000 + i, v, 19);
      27    }
      28  
      29    for (int i = 0 ; i < n * n; i++) {
      30      vint32m1_t v = __riscv_vle32_v_i32m1 (in + 2000 + i, 8);
      31      __riscv_vse32_v_i32m1 (out + 2000 + i, v, 8);
      32    }
      33  
      34    for (int i = 0 ; i < n * n * n; i++) {
      35      vint16mf2_t v = __riscv_vle16_v_i16mf2 (in + 3000 + i, 8);
      36      __riscv_vse16_v_i16mf2 (out + 3000 + i, v, 8);
      37    }
      38  }
      39  
      40  /* { dg-final { scan-assembler {vsetivli\s+zero,\s*5,\s*e8,\s*mf8,\s*tu,\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      41  /* { dg-final { scan-assembler {vsetivli\s+zero,\s*19,\s*e32,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      42  /* { dg-final { scan-assembler {vsetivli\s+zero,\s*8,\s*e32,\s*m1,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      43  /* { dg-final { scan-assembler {vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz"  no-opts "-funroll-loops" no-opts "-g" } } } } */