1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-tree-vectorize -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f(void *base, void *out, void *mask_in, size_t vl, size_t m, size_t n) {
       7    vbool64_t mask = *(vbool64_t*)mask_in;
       8  
       9    for (size_t i = 0; i < m; i++) {
      10      for (size_t j = 0; j < n; j++){
      11        if ((i + j) % 2 == 0) {
      12          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j, 4);
      13          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 100, 4);
      14          __riscv_vse8_v_i8mf8 (out + i + j, v1, 4);
      15        } else {
      16          vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j, 4);
      17          vint16mf4_t v1 = __riscv_vle16_v_i16mf4_mu(mask, v0, base + i + j + 100, 4);
      18          __riscv_vse16_v_i16mf4 (out + i + j, v1, 4);
      19        }
      20      }
      21    }
      22  }
      23  
      24  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*4,\s*e8,\s*mf8,\s*tu,\s*mu} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      25