1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (void * restrict in, void * restrict out, int l, int n, int m, size_t vl)
       7  {
       8    for (int i = 0; i < l; i++){
       9      vl++;
      10      for (int j = 0; j < m; j++){
      11        for (int k = 0; k < n; k++)
      12          {
      13            vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + j + k, vl);
      14            __riscv_vse8_v_i8mf8 (out + i + j + k, v, vl);
      15          }
      16      }
      17    }
      18  }
      19  
      20  /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      21  /* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      22  /* { dg-final { scan-assembler-times {add\s+\s*[a-x0-9]+,\s*[a-x0-9]+,\s*[a-x0-9]+\s+li\s+[a-x0-9]+,0\s+vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-O2" no-opts "-g" no-opts "-funroll-loops" } } } } */