1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
       7    
       8    size_t vl = 333;
       9    for (size_t i = 0; i < m; i++) {
      10      if (i % 2 == 0) {
      11        for (size_t j = 0; j < n; j++){
      12          if (j % 2 == 0) {
      13            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 200, vl);
      14            vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 200, vl);
      15            __riscv_vse8_v_i8mf8 (out + i + 200, v1, vl);
      16          } else {
      17            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + 300, vl);
      18            vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + 300, vl);
      19            __riscv_vse8_v_i8mf8 (out + i + 300, v1, vl);
      20          }
      21        }
      22      } else {
      23        for (size_t j = 0; j < n; j++){
      24          vint8mf8_t v1 = __riscv_vle8_v_i8mf8(base + i + j + 300, vl);
      25          __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, vl);
      26        }
      27      }
      28    }
      29  }
      30  
      31  /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      32  /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */