1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f(void *base, void *out, void *mask_in, size_t m, size_t n) {
       7    
       8    size_t vl = 107;
       9    for (size_t i = 0; i < m; i++) {
      10      if (i % 2 == 0) {
      11        for (size_t j = 0; j < n; j++){
      12          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 700, vl);
      13          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 700, vl);
      14          __riscv_vse8_v_i8mf8 (out + i + j + 700, v1, vl);
      15          if (j % 2 == 0) {
      16            vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 500, vl);
      17            __riscv_vse8_v_i8mf8 (out + i + j + 500, v0, vl);
      18          } else {
      19            vint16mf4_t v0 = __riscv_vle16_v_i16mf4(base + i + j + 600, vl);
      20            __riscv_vse16_v_i16mf4 (out + i + j + 600, v0, vl);
      21          }
      22        }
      23      } else {
      24        for (size_t j = 0; j < n; j++){
      25          vint8mf8_t v0 = __riscv_vle8_v_i8mf8(base + i + j + 200, vl);
      26          vint8mf8_t v1 = __riscv_vle8_v_i8mf8_tu(v0, base + i + j + 300, vl);
      27          __riscv_vse8_v_i8mf8 (out + i + j + 400, v1, vl);
      28        }
      29      }
      30    }
      31  }
      32  
      33  /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */
      34  /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */