1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (int8_t * restrict in, int8_t * restrict out, int8_t * restrict out2, int n, int m, unsigned cond, size_t vl)
       7  {
       8    vl = 22;
       9    vbool64_t mask = *(vbool64_t*) (in + 1000000);
      10    if (cond == 0) {
      11      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
      12      __riscv_vse8_v_i8mf8 (out, v, vl);
      13    } else {
      14      out2[100] = out2[100] + 300;
      15    }
      16  
      17    for (size_t i = 0; i < n; i++)
      18      out[i + 200] = out[i + 500] + 22;
      19  
      20    for (size_t i = 0; i < n; i++)
      21      {
      22        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), 22);
      23        __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, 22);
      24        
      25        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), 22);
      26        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, 22);
      27      }
      28  }
      29  
      30  void f2 (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl)
      31  {
      32    asm volatile ("li %0, 101" :"=r" (vl)::"memory");
      33    vbool64_t mask = *(vbool64_t*) (in + 1000000);
      34    if (cond > 0) {
      35      vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, vl);
      36      __riscv_vse8_v_i8mf8 (out, v, vl);
      37    } else {
      38      out[100] = out[100] + 300;
      39    }
      40  
      41    for (size_t i = 0; i < n; i++)
      42      out[i + 200] = out[i + 500] + 555;
      43  
      44    for (size_t i = 0; i < n; i++)
      45      {
      46        vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((float *)(in + i + 200), vl);
      47        __riscv_vse32_v_f32mf2 ((float *)(out + i + 200), v, vl);
      48        
      49        vfloat32mf2_t v2 = __riscv_vle32_v_f32mf2_tumu (mask, v, (float *)(in + i + 300), vl);
      50        __riscv_vse32_v_f32mf2_m (mask, (float *)(out + i + 300), v2, vl);
      51      }
      52  }
      53  
      54  /* { dg-final { scan-assembler-times {vsetivli\s+zero,22,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      55  /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu} 2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      56  /* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      57  /* { dg-final { scan-assembler-times {vsetivli} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */