1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -fno-tree-vectorize -frename-registers" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (int8_t * restrict in, int8_t * restrict out, int n, int m, unsigned cond, size_t vl, double scalar)
       7  {
       8    size_t new_vl = 101;
       9    
      10    if  (m > n) {
      11    vfloat64m4_t v2 = __riscv_vle64_v_f64m4 ((double *)in, new_vl);
      12    double f = __riscv_vfmv_f_s_f64m4_f64 (v2);
      13    
      14    for (size_t i = 0; i < n; i++)
      15      {
      16        vfloat64m4_t v3 = __riscv_vle64_v_f64m4 ((double *)(in + i + 500), new_vl);
      17        vfloat64m4_t v4 = __riscv_vle64_v_f64m4 ((double *)(in + i + 600), new_vl);
      18        v4 = __riscv_vfmacc_vf_f64m4 (v4, f, v3, new_vl);
      19        
      20        __riscv_vse64_v_f64m4 ((double *)(out + i + 200), v4, new_vl);
      21      }
      22    } else {
      23      ;
      24    }
      25  }
      26  
      27  /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-O1" no-opts "-g" no-opts "-funroll-loops" } } } } */
      28  /* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */
      29  /* { dg-final { scan-assembler-not {vsetivli} { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-g" no-opts "-funroll-loops" } } } } */