1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (void * restrict in, void * restrict out, int n, int cond)
       7  {
       8    size_t vl;
       9    switch (cond)
      10    {
      11    case 1:
      12      vl = 100;
      13      break;
      14    case 2:
      15      vl = *(size_t*)(in + 100);
      16      break;
      17    case 3:
      18      {
      19        size_t new_vl = *(size_t*)(in + 500);
      20        size_t new_vl2 = *(size_t*)(in + 600);
      21        vl = new_vl + new_vl2 + 777;
      22        break;
      23      }
      24    default:
      25      break;
      26    }
      27    for (int i = 0; i < n; i++)
      28      {
      29        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
      30        __riscv_vse8_v_i8mf8 (out + i, v, vl);
      31      }
      32  }
      33  
      34  /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */
      35  /* { dg-final { scan-assembler {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]} { target { no-opts "-O0" no-opts "-g" no-opts "-funroll-loops" } } } } */