1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (void * restrict in, void * restrict out, int n, int cond)
       7  {
       8    size_t vl;
       9    switch (cond)
      10    {
      11    case 1:
      12      vl = 100;
      13      break;
      14    case 2:
      15      vl = *(size_t*)(in + 100);
      16      break;
      17    case 3:
      18      {
      19        size_t new_vl = *(size_t*)(in + 500);
      20        size_t new_vl2 = *(size_t*)(in + 600);
      21        vl = new_vl + new_vl2 + 777;
      22        break;
      23      }
      24    default:
      25      vl = vl + 4000;
      26      break;
      27    }
      28    for (size_t i = 0; i < n; i++)
      29      {
      30        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
      31        __riscv_vse8_v_i8mf8 (out + i, v, vl);
      32        
      33        vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 100, vl);
      34        __riscv_vse8_v_i8mf8 (out + i + 100, v2, vl);
      35      }
      36    
      37    for (size_t i = 0; i < n; i++)
      38      {
      39        vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i + 300, vl);
      40        __riscv_vse8_v_i8mf8 (out + i + 300, v, vl);
      41        vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in + i + 200, vl);
      42        __riscv_vse8_v_i8mf8 (out + i + 200, v2, vl);
      43      }
      44  }
      45  
      46  /* { dg-final { scan-assembler-times {\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,\s*0\s*\([a-x0-9]+\)} 2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-g" no-opts "-funroll-loops" } } } } */