1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gcv -mabi=ilp32 -O3" } */
3 /* { dg-final { check-function-bodies "**" "" } } */
4 #include "riscv_vector.h"
5
6 /*
7 ** f0:
8 ** ...
9 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
10 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
11 ** ...
12 ** ret
13 */
14 void f0 (void * in, void *out, int64_t x, int n)
15 {
16 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
17 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
18 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
19 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask, v2, -16, v2, 4);
20 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask, v3, -16, v3, 4);
21 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
22 }
23
24 /*
25 ** f1:
26 ** ...
27 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
28 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
29 ** ...
30 ** ret
31 */
32 void f1 (void * in, void *out, int64_t x, int n)
33 {
34 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
35 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
36 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
37 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask,v2, 15, v2, 4);
38 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask,v3, 15, v3, 4);
39 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
40 }
41
42 /*
43 ** f2:
44 ** ...
45 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
46 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
47 ** ...
48 ** ret
49 */
50 void f2 (void * in, void *out, int64_t x, int n)
51 {
52 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
53 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
54 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
55 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask,v2, 16, v2, 4);
56 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask,v3, 16, v3, 4);
57 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
58 }
59
60 /*
61 ** f3:
62 ** ...
63 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
64 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
65 ** ...
66 ** ret
67 */
68 void f3 (void * in, void *out, int64_t x, int n)
69 {
70 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
71 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
72 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
73 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask,v2, 0xAAAAAA, v2, 4);
74 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask,v3, 0xAAAAAA, v3, 4);
75 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
76 }
77
78 /*
79 ** f4:
80 ** ...
81 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
82 ** vma[c-d][c-d]\.vx\tv[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+,v0.t
83 ** ...
84 ** ret
85 */
86 void f4 (void * in, void *out, int64_t x, int n)
87 {
88 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
89 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
90 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
91 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask,v2, 0xAAAAAAA, v2, 4);
92 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask,v3, 0xAAAAAAA, v3, 4);
93 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
94 }
95
96 /*
97 ** f5:
98 ** ...
99 ** vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,v0.t
100 ** vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,v0.t
101 ** ...
102 */
103 void f5 (void * in, void *out, int64_t x, int n)
104 {
105 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
106 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
107 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
108 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask,v2, 0xAAAAAAAAAAAAAAAA, v2, 4);
109 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask,v3, 0xAAAAAAAAAAAAAAAA, v3, 4);
110 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
111 }
112
113 /*
114 ** f6:
115 ** ...
116 ** vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,v0.t
117 ** vma[c-d][c-d]\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,v0.t
118 ** ...
119 */
120 void f6 (void * in, void *out, int64_t x, int n)
121 {
122 vbool64_t mask = __riscv_vlm_v_b64 (in + 100, 4);
123 vint64m1_t v = __riscv_vle64_v_i64m1 (in + 1, 4);
124 vint64m1_t v2 = __riscv_vle64_v_i64m1_tu (v, in + 2, 4);
125 vint64m1_t v3 = __riscv_vmacc_vx_i64m1_tumu (mask,v2, x, v2, 4);
126 vint64m1_t v4 = __riscv_vmacc_vx_i64m1_tumu (mask,v3, x, v3, 4);
127 __riscv_vse64_v_i64m1 (out + 2, v4, 4);
128 }
129
130 /* { dg-final { scan-assembler-not {vmv} } } */