1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
       3  /* { dg-final { check-function-bodies "**" "" } } */
       4  
       5  #include "riscv_vector.h"
       6  
       7  void f (char*);
       8  
       9  /*
      10  ** stach_check_alloca_1:
      11  **	addi\tsp,sp,-48
      12  **	sw\tra,12\(sp\)
      13  **	sw\ts0,8\(sp\)
      14  **	addi\ts0,sp,16
      15  **	csrr\tt0,vlenb
      16  **	slli\tt1,t0,1
      17  **	sub\tsp,sp,t1
      18  **	...
      19  **	addi\ta2,a2,23
      20  **	andi\ta2,a2,-16
      21  **	sub\tsp,sp,a2
      22  **	...
      23  **	lw\tra,12\(sp\)
      24  **	lw\ts0,8\(sp\)
      25  **	addi\tsp,sp,48
      26  **	jr\tra
      27  */
      28  void stach_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...)
      29  {
      30    vuint8m8_t v0, v8, v16, v24;
      31    asm volatile ("nop"
      32                  : "=vr" (v0), "=vr" (v8), "=vr" (v16), "=vr" (v24)
      33                  :
      34                  :);
      35    asm volatile ("nop"
      36                  :
      37                  : "vr" (v0), "vr" (v8), "vr" (v16), "vr" (v24)
      38                  :);
      39    *(vuint8m1_t *)base = data;
      40    char* pStr = (char*)__builtin_alloca(y);
      41    f(pStr);
      42  }