1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
       3  /* { dg-final { check-function-bodies "**" "" } } */
       4  
       5  #include "riscv_vector.h"
       6  #include "macro.h"
       7  
       8  /*
       9  ** spill_4:
      10  **  csrr\tt0,vlenb
      11  **  sub\tsp,sp,t0
      12  **  ...
      13  **  vs1r.v\tv24,0\(sp\)
      14  **  ...
      15  **  vl1re64.v\tv2,0\(sp\)
      16  **  vs1r.v\tv2,0\(a1\)
      17  **  ...
      18  **  jr\tra
      19  */
      20  void
      21  spill_4 (double *in, double *out)
      22  {
      23    register vfloat64m1_t v1 asm("v1") = *(vfloat64m1_t*)in; 
      24    asm volatile ("# %0"::"vr"(v1)); 
      25    exhaust_vector_regs (); 
      26    register vfloat64m1_t v2 asm("v2") = v1; 
      27    *(vfloat64m1_t*)out = v2; 
      28    asm volatile ("# %0"::"vr"(v2));
      29  }
      30  
      31  /*
      32  ** spill_5:
      33  **  csrr\tt0,vlenb
      34  **  slli\tt1,t0,1
      35  **  sub\tsp,sp,t1
      36  **  ...
      37  **  vs2r.v\tv24,0\(sp\)
      38  **  ...
      39  **  vl2re64.v\tv4,0\(sp\)
      40  **  vs2r.v\tv4,0\(a1\)
      41  **  ...
      42  **  jr\tra
      43  */
      44  void
      45  spill_5 (double *in, double *out)
      46  {
      47    register vfloat64m2_t v2 asm("v2") = *(vfloat64m2_t*)in; 
      48    asm volatile ("# %0"::"vr"(v2)); 
      49    exhaust_vector_regs (); 
      50    register vfloat64m2_t v4 asm("v4") = v2; 
      51    *(vfloat64m2_t*)out = v4; 
      52    asm volatile ("# %0"::"vr"(v4));
      53  }
      54  
      55  /*
      56  ** spill_6:
      57  **  csrr\tt0,vlenb
      58  **  slli\tt1,t0,2
      59  **  sub\tsp,sp,t1
      60  **  ...
      61  **  vs4r.v\tv24,0\(sp\)
      62  **  ...
      63  **  vl4re64.v\tv8,0\(sp\)
      64  **  vs4r.v\tv8,0\(a1\)
      65  **  ...
      66  **  jr\tra
      67  */
      68  void
      69  spill_6 (double *in, double *out)
      70  {
      71    register vfloat64m4_t v4 asm("v4") = *(vfloat64m4_t*)in; 
      72    asm volatile ("# %0"::"vr"(v4)); 
      73    exhaust_vector_regs (); 
      74    register vfloat64m4_t v8 asm("v8") = v4; 
      75    *(vfloat64m4_t*)out = v8; 
      76    asm volatile ("# %0"::"vr"(v8));
      77  }
      78  
      79  /*
      80  ** spill_7:
      81  **  csrr\tt0,vlenb
      82  **  slli\tt1,t0,3
      83  **  sub\tsp,sp,t1
      84  **  ...
      85  **  vs8r.v\tv24,0\(sp\)
      86  **  ...
      87  **  vl8re64.v\tv16,0\(sp\)
      88  **  vs8r.v\tv16,0\(a1\)
      89  **  ...
      90  **  jr\tra
      91  */
      92  void
      93  spill_7 (double *in, double *out)
      94  {
      95    register vfloat64m8_t v8 asm("v8") = *(vfloat64m8_t*)in; 
      96    asm volatile ("# %0"::"vr"(v8)); 
      97    exhaust_vector_regs (); 
      98    register vfloat64m8_t v16 asm("v16") = v8; 
      99    *(vfloat64m8_t*)out = v16; 
     100    asm volatile ("# %0"::"vr"(v16));
     101  }