1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
       3  /* { dg-final { check-function-bodies "**" "" } } */
       4  
       5  #include "riscv_vector.h"
       6  #include "macro.h"
       7  
       8  /*
       9  ** spill_3:
      10  **  csrr\tt0,vlenb
      11  **  sub\tsp,sp,t0
      12  **  vsetvli\ta5,zero,e32,mf2,ta,ma
      13  **  vle32.v\tv[0-9]+,0\(a0\)
      14  **  csrr\t[a-x0-9]+,vlenb
      15  **  srli\t[a-x0-9]+,[a-x0-9]+,1
      16  **  add\t[a-x0-9]+,[a-x0-9]+,sp
      17  **  vse32.v\tv[0-9]+,0\([a-x0-9]+\)
      18  **  ...
      19  **  csrr\t[a-x0-9]+,vlenb
      20  **  srli\t[a-x0-9]+,[a-x0-9]+,1
      21  **  add\t[a-x0-9]+,[a-x0-9]+,sp
      22  **  vle32.v\tv[0-9]+,0\([a-x0-9]+\)
      23  **  vse32.v\tv[0-9]+,0\([a-x0-9]+\)
      24  **  csrr\tt0,vlenb
      25  **  add\tsp,sp,t0
      26  **  ...
      27  **  jr\tra
      28  */
      29  void
      30  spill_3 (float *in, float *out)
      31  {
      32    vfloat32mf2_t v1 = *(vfloat32mf2_t*)in;
      33    exhaust_vector_regs ();
      34    *(vfloat32mf2_t*)out = v1;
      35  }
      36  
      37  /*
      38  ** spill_4:
      39  **  csrr\tt0,vlenb
      40  **  sub\tsp,sp,t0
      41  **  ...
      42  **  vs1r.v\tv[0-9]+,0\(sp\)
      43  **  ...
      44  **  vl1re32.v\tv2,0\(sp\)
      45  **  vs1r.v\tv2,0\([a-x0-9]+\)
      46  **  ...
      47  **  jr\tra
      48  */
      49  void
      50  spill_4 (float *in, float *out)
      51  {
      52    register vfloat32m1_t v1 asm("v1") = *(vfloat32m1_t*)in; 
      53    asm volatile ("# %0"::"vr"(v1)); 
      54    exhaust_vector_regs (); 
      55    register vfloat32m1_t v2 asm("v2") = v1; 
      56    *(vfloat32m1_t*)out = v2; 
      57    asm volatile ("# %0"::"vr"(v2));
      58  }
      59  
      60  /*
      61  ** spill_5:
      62  **  csrr\tt0,vlenb
      63  **  slli\tt1,t0,1
      64  **  sub\tsp,sp,t1
      65  **  ...
      66  **  vs2r.v\tv[0-9]+,0\(sp\)
      67  **  ...
      68  **  vl2re32.v\tv4,0\(sp\)
      69  **  vs2r.v\tv4,0\([a-x0-9]+\)
      70  **  ...
      71  **  jr\tra
      72  */
      73  void
      74  spill_5 (float *in, float *out)
      75  {
      76    register vfloat32m2_t v2 asm("v2") = *(vfloat32m2_t*)in; 
      77    asm volatile ("# %0"::"vr"(v2)); 
      78    exhaust_vector_regs (); 
      79    register vfloat32m2_t v4 asm("v4") = v2; 
      80    *(vfloat32m2_t*)out = v4; 
      81    asm volatile ("# %0"::"vr"(v4));
      82  }
      83  
      84  /*
      85  ** spill_6:
      86  **  csrr\tt0,vlenb
      87  **  slli\tt1,t0,2
      88  **  sub\tsp,sp,t1
      89  **  ...
      90  **  vs4r.v\tv[0-9]+,0\(sp\)
      91  **  ...
      92  **  vl4re32.v\tv8,0\(sp\)
      93  **  vs4r.v\tv8,0\([a-x0-9]+\)
      94  **  ...
      95  **  jr\tra
      96  */
      97  void
      98  spill_6 (float *in, float *out)
      99  {
     100    register vfloat32m4_t v4 asm("v4") = *(vfloat32m4_t*)in; 
     101    asm volatile ("# %0"::"vr"(v4)); 
     102    exhaust_vector_regs (); 
     103    register vfloat32m4_t v8 asm("v8") = v4; 
     104    *(vfloat32m4_t*)out = v8; 
     105    asm volatile ("# %0"::"vr"(v8));
     106  }
     107  
     108  /*
     109  ** spill_7:
     110  **  csrr\tt0,vlenb
     111  **  slli\tt1,t0,3
     112  **  sub\tsp,sp,t1
     113  **  ...
     114  **  vs8r.v\tv[0-9]+,0\(sp\)
     115  **  ...
     116  **  vl8re32.v\tv16,0\(sp\)
     117  **  vs8r.v\tv16,0\([a-x0-9]+\)
     118  **  ...
     119  **  jr\tra
     120  */
     121  void
     122  spill_7 (float *in, float *out)
     123  {
     124    register vfloat32m8_t v8 asm("v8") = *(vfloat32m8_t*)in; 
     125    asm volatile ("# %0"::"vr"(v8)); 
     126    exhaust_vector_regs (); 
     127    register vfloat32m8_t v16 asm("v16") = v8; 
     128    *(vfloat32m8_t*)out = v16; 
     129    asm volatile ("# %0"::"vr"(v16));
     130  }