1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
3 /* { dg-final { check-function-bodies "**" "" } } */
4
5 #include "riscv_vector.h"
6 #include "macro.h"
7
8 /*
9 ** spill_4:
10 ** csrr\tt0,vlenb
11 ** sub\tsp,sp,t0
12 ** ...
13 ** vs1r.v\tv24,0\(sp\)
14 ** ...
15 ** vl1re64.v\tv2,0\(sp\)
16 ** vs1r.v\tv2,0\(a1\)
17 ** ...
18 ** jr\tra
19 */
20 void
21 spill_4 (int64_t *in, int64_t *out)
22 {
23 register vint64m1_t v1 asm("v1") = *(vint64m1_t*)in;
24 asm volatile ("# %0"::"vr"(v1));
25 exhaust_vector_regs ();
26 register vint64m1_t v2 asm("v2") = v1;
27 *(vint64m1_t*)out = v2;
28 asm volatile ("# %0"::"vr"(v2));
29 }
30
31 /*
32 ** spill_5:
33 ** csrr\tt0,vlenb
34 ** slli\tt1,t0,1
35 ** sub\tsp,sp,t1
36 ** ...
37 ** vs2r.v\tv24,0\(sp\)
38 ** ...
39 ** vl2re64.v\tv4,0\(sp\)
40 ** vs2r.v\tv4,0\(a1\)
41 ** ...
42 ** jr\tra
43 */
44 void
45 spill_5 (int64_t *in, int64_t *out)
46 {
47 register vint64m2_t v2 asm("v2") = *(vint64m2_t*)in;
48 asm volatile ("# %0"::"vr"(v2));
49 exhaust_vector_regs ();
50 register vint64m2_t v4 asm("v4") = v2;
51 *(vint64m2_t*)out = v4;
52 asm volatile ("# %0"::"vr"(v4));
53 }
54
55 /*
56 ** spill_6:
57 ** csrr\tt0,vlenb
58 ** slli\tt1,t0,2
59 ** sub\tsp,sp,t1
60 ** ...
61 ** vs4r.v\tv24,0\(sp\)
62 ** ...
63 ** vl4re64.v\tv8,0\(sp\)
64 ** vs4r.v\tv8,0\(a1\)
65 ** ...
66 ** jr\tra
67 */
68 void
69 spill_6 (int64_t *in, int64_t *out)
70 {
71 register vint64m4_t v4 asm("v4") = *(vint64m4_t*)in;
72 asm volatile ("# %0"::"vr"(v4));
73 exhaust_vector_regs ();
74 register vint64m4_t v8 asm("v8") = v4;
75 *(vint64m4_t*)out = v8;
76 asm volatile ("# %0"::"vr"(v8));
77 }
78
79 /*
80 ** spill_7:
81 ** csrr\tt0,vlenb
82 ** slli\tt1,t0,3
83 ** sub\tsp,sp,t1
84 ** ...
85 ** vs8r.v\tv24,0\(sp\)
86 ** ...
87 ** vl8re64.v\tv16,0\(sp\)
88 ** vs8r.v\tv16,0\(a1\)
89 ** ...
90 ** jr\tra
91 */
92 void
93 spill_7 (int64_t *in, int64_t *out)
94 {
95 register vint64m8_t v8 asm("v8") = *(vint64m8_t*)in;
96 asm volatile ("# %0"::"vr"(v8));
97 exhaust_vector_regs ();
98 register vint64m8_t v16 asm("v16") = v8;
99 *(vint64m8_t*)out = v16;
100 asm volatile ("# %0"::"vr"(v16));
101 }
102
103 /*
104 ** spill_11:
105 ** csrr\tt0,vlenb
106 ** sub\tsp,sp,t0
107 ** ...
108 ** vs1r.v\tv24,0\(sp\)
109 ** ...
110 ** vl1re64.v\tv2,0\(sp\)
111 ** vs1r.v\tv2,0\(a1\)
112 ** ...
113 ** jr\tra
114 */
115 void
116 spill_11 (uint64_t *in, uint64_t *out)
117 {
118 register vuint64m1_t v1 asm("v1") = *(vuint64m1_t*)in;
119 asm volatile ("# %0"::"vr"(v1));
120 exhaust_vector_regs ();
121 register vuint64m1_t v2 asm("v2") = v1;
122 *(vuint64m1_t*)out = v2;
123 asm volatile ("# %0"::"vr"(v2));
124 }
125
126 /*
127 ** spill_12:
128 ** csrr\tt0,vlenb
129 ** slli\tt1,t0,1
130 ** sub\tsp,sp,t1
131 ** ...
132 ** vs2r.v\tv24,0\(sp\)
133 ** ...
134 ** vl2re64.v\tv4,0\(sp\)
135 ** vs2r.v\tv4,0\(a1\)
136 ** ...
137 ** jr\tra
138 */
139 void
140 spill_12 (uint64_t *in, uint64_t *out)
141 {
142 register vuint64m2_t v2 asm("v2") = *(vuint64m2_t*)in;
143 asm volatile ("# %0"::"vr"(v2));
144 exhaust_vector_regs ();
145 register vuint64m2_t v4 asm("v4") = v2;
146 *(vuint64m2_t*)out = v4;
147 asm volatile ("# %0"::"vr"(v4));
148 }
149
150 /*
151 ** spill_13:
152 ** csrr\tt0,vlenb
153 ** slli\tt1,t0,2
154 ** sub\tsp,sp,t1
155 ** ...
156 ** vs4r.v\tv24,0\(sp\)
157 ** ...
158 ** vl4re64.v\tv8,0\(sp\)
159 ** vs4r.v\tv8,0\(a1\)
160 ** ...
161 ** jr\tra
162 */
163 void
164 spill_13 (uint64_t *in, uint64_t *out)
165 {
166 register vuint64m4_t v4 asm("v4") = *(vuint64m4_t*)in;
167 asm volatile ("# %0"::"vr"(v4));
168 exhaust_vector_regs ();
169 register vuint64m4_t v8 asm("v8") = v4;
170 *(vuint64m4_t*)out = v8;
171 asm volatile ("# %0"::"vr"(v8));
172 }
173
174 /*
175 ** spill_14:
176 ** csrr\tt0,vlenb
177 ** slli\tt1,t0,3
178 ** sub\tsp,sp,t1
179 ** ...
180 ** vs8r.v\tv24,0\(sp\)
181 ** ...
182 ** vl8re64.v\tv16,0\(sp\)
183 ** vs8r.v\tv16,0\(a1\)
184 ** ...
185 ** jr\tra
186 */
187 void
188 spill_14 (uint64_t *in, uint64_t *out)
189 {
190 register vuint64m8_t v8 asm("v8") = *(vuint64m8_t*)in;
191 asm volatile ("# %0"::"vr"(v8));
192 exhaust_vector_regs ();
193 register vuint64m8_t v16 asm("v16") = v8;
194 *(vuint64m8_t*)out = v16;
195 asm volatile ("# %0"::"vr"(v16));
196 }