1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
3 /* { dg-final { check-function-bodies "**" "" } } */
4
5 #include "riscv_vector.h"
6 #include "macro.h"
7
8 /*
9 ** spill_3:
10 ** csrr\tt0,vlenb
11 ** sub\tsp,sp,t0
12 ** vsetvli\ta5,zero,e32,mf2,ta,ma
13 ** vle32.v\tv[0-9]+,0\(a0\)
14 ** csrr\t[a-x0-9]+,vlenb
15 ** srli\t[a-x0-9]+,[a-x0-9]+,1
16 ** add\t[a-x0-9]+,[a-x0-9]+,sp
17 ** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
18 ** ...
19 ** csrr\t[a-x0-9]+,vlenb
20 ** srli\t[a-x0-9]+,[a-x0-9]+,1
21 ** add\t[a-x0-9]+,[a-x0-9]+,sp
22 ** vle32.v\tv[0-9]+,0\([a-x0-9]+\)
23 ** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
24 ** csrr\tt0,vlenb
25 ** add\tsp,sp,t0
26 ** ...
27 ** jr\tra
28 */
29 void
30 spill_3 (int32_t *in, int32_t *out)
31 {
32 vint32mf2_t v1 = *(vint32mf2_t*)in;
33 exhaust_vector_regs ();
34 *(vint32mf2_t*)out = v1;
35 }
36
37 /*
38 ** spill_4:
39 ** csrr\tt0,vlenb
40 ** sub\tsp,sp,t0
41 ** ...
42 ** vs1r.v\tv[0-9]+,0\(sp\)
43 ** ...
44 ** vl1re32.v\tv2,0\(sp\)
45 ** vs1r.v\tv2,0\([a-x0-9]+\)
46 ** ...
47 ** jr\tra
48 */
49 void
50 spill_4 (int32_t *in, int32_t *out)
51 {
52 register vint32m1_t v1 asm("v1") = *(vint32m1_t*)in;
53 asm volatile ("# %0"::"vr"(v1));
54 exhaust_vector_regs ();
55 register vint32m1_t v2 asm("v2") = v1;
56 *(vint32m1_t*)out = v2;
57 asm volatile ("# %0"::"vr"(v2));
58 }
59
60 /*
61 ** spill_5:
62 ** csrr\tt0,vlenb
63 ** slli\tt1,t0,1
64 ** sub\tsp,sp,t1
65 ** ...
66 ** vs2r.v\tv[0-9]+,0\(sp\)
67 ** ...
68 ** vl2re32.v\tv4,0\(sp\)
69 ** vs2r.v\tv4,0\([a-x0-9]+\)
70 ** ...
71 ** jr\tra
72 */
73 void
74 spill_5 (int32_t *in, int32_t *out)
75 {
76 register vint32m2_t v2 asm("v2") = *(vint32m2_t*)in;
77 asm volatile ("# %0"::"vr"(v2));
78 exhaust_vector_regs ();
79 register vint32m2_t v4 asm("v4") = v2;
80 *(vint32m2_t*)out = v4;
81 asm volatile ("# %0"::"vr"(v4));
82 }
83
84 /*
85 ** spill_6:
86 ** csrr\tt0,vlenb
87 ** slli\tt1,t0,2
88 ** sub\tsp,sp,t1
89 ** ...
90 ** vs4r.v\tv[0-9]+,0\(sp\)
91 ** ...
92 ** vl4re32.v\tv8,0\(sp\)
93 ** vs4r.v\tv8,0\([a-x0-9]+\)
94 ** ...
95 ** jr\tra
96 */
97 void
98 spill_6 (int32_t *in, int32_t *out)
99 {
100 register vint32m4_t v4 asm("v4") = *(vint32m4_t*)in;
101 asm volatile ("# %0"::"vr"(v4));
102 exhaust_vector_regs ();
103 register vint32m4_t v8 asm("v8") = v4;
104 *(vint32m4_t*)out = v8;
105 asm volatile ("# %0"::"vr"(v8));
106 }
107
108 /*
109 ** spill_7:
110 ** csrr\tt0,vlenb
111 ** slli\tt1,t0,3
112 ** sub\tsp,sp,t1
113 ** ...
114 ** vs8r.v\tv[0-9]+,0\(sp\)
115 ** ...
116 ** vl8re32.v\tv16,0\(sp\)
117 ** vs8r.v\tv16,0\([a-x0-9]+\)
118 ** ...
119 ** jr\tra
120 */
121 void
122 spill_7 (int32_t *in, int32_t *out)
123 {
124 register vint32m8_t v8 asm("v8") = *(vint32m8_t*)in;
125 asm volatile ("# %0"::"vr"(v8));
126 exhaust_vector_regs ();
127 register vint32m8_t v16 asm("v16") = v8;
128 *(vint32m8_t*)out = v16;
129 asm volatile ("# %0"::"vr"(v16));
130 }
131
132 /*
133 ** spill_10:
134 ** csrr\tt0,vlenb
135 ** sub\tsp,sp,t0
136 ** vsetvli\ta5,zero,e32,mf2,ta,ma
137 ** vle32.v\tv[0-9]+,0\(a0\)
138 ** csrr\t[a-x0-9]+,vlenb
139 ** srli\t[a-x0-9]+,[a-x0-9]+,1
140 ** add\t[a-x0-9]+,[a-x0-9]+,sp
141 ** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
142 ** ...
143 ** csrr\t[a-x0-9]+,vlenb
144 ** srli\t[a-x0-9]+,[a-x0-9]+,1
145 ** add\t[a-x0-9]+,[a-x0-9]+,sp
146 ** vle32.v\tv[0-9]+,0\([a-x0-9]+\)
147 ** vse32.v\tv[0-9]+,0\([a-x0-9]+\)
148 ** csrr\tt0,vlenb
149 ** add\tsp,sp,t0
150 ** ...
151 ** jr\tra
152 */
153 void
154 spill_10 (uint32_t *in, uint32_t *out)
155 {
156 vuint32mf2_t v1 = *(vuint32mf2_t*)in;
157 exhaust_vector_regs ();
158 *(vuint32mf2_t*)out = v1;
159 }
160
161 /*
162 ** spill_11:
163 ** csrr\tt0,vlenb
164 ** sub\tsp,sp,t0
165 ** ...
166 ** vs1r.v\tv[0-9]+,0\(sp\)
167 ** ...
168 ** vl1re32.v\tv2,0\(sp\)
169 ** vs1r.v\tv2,0\([a-x0-9]+\)
170 ** ...
171 ** jr\tra
172 */
173 void
174 spill_11 (uint32_t *in, uint32_t *out)
175 {
176 register vuint32m1_t v1 asm("v1") = *(vuint32m1_t*)in;
177 asm volatile ("# %0"::"vr"(v1));
178 exhaust_vector_regs ();
179 register vuint32m1_t v2 asm("v2") = v1;
180 *(vuint32m1_t*)out = v2;
181 asm volatile ("# %0"::"vr"(v2));
182 }
183
184 /*
185 ** spill_12:
186 ** csrr\tt0,vlenb
187 ** slli\tt1,t0,1
188 ** sub\tsp,sp,t1
189 ** ...
190 ** vs2r.v\tv[0-9]+,0\(sp\)
191 ** ...
192 ** vl2re32.v\tv4,0\(sp\)
193 ** vs2r.v\tv4,0\([a-x0-9]+\)
194 ** ...
195 ** jr\tra
196 */
197 void
198 spill_12 (uint32_t *in, uint32_t *out)
199 {
200 register vuint32m2_t v2 asm("v2") = *(vuint32m2_t*)in;
201 asm volatile ("# %0"::"vr"(v2));
202 exhaust_vector_regs ();
203 register vuint32m2_t v4 asm("v4") = v2;
204 *(vuint32m2_t*)out = v4;
205 asm volatile ("# %0"::"vr"(v4));
206 }
207
208 /*
209 ** spill_13:
210 ** csrr\tt0,vlenb
211 ** slli\tt1,t0,2
212 ** sub\tsp,sp,t1
213 ** ...
214 ** vs4r.v\tv[0-9]+,0\(sp\)
215 ** ...
216 ** vl4re32.v\tv8,0\(sp\)
217 ** vs4r.v\tv8,0\([a-x0-9]+\)
218 ** ...
219 ** jr\tra
220 */
221 void
222 spill_13 (uint32_t *in, uint32_t *out)
223 {
224 register vuint32m4_t v4 asm("v4") = *(vuint32m4_t*)in;
225 asm volatile ("# %0"::"vr"(v4));
226 exhaust_vector_regs ();
227 register vuint32m4_t v8 asm("v8") = v4;
228 *(vuint32m4_t*)out = v8;
229 asm volatile ("# %0"::"vr"(v8));
230 }
231
232 /*
233 ** spill_14:
234 ** csrr\tt0,vlenb
235 ** slli\tt1,t0,3
236 ** sub\tsp,sp,t1
237 ** ...
238 ** vs8r.v\tv[0-9]+,0\(sp\)
239 ** ...
240 ** vl8re32.v\tv16,0\(sp\)
241 ** vs8r.v\tv16,0\([a-x0-9]+\)
242 ** ...
243 ** jr\tra
244 */
245 void
246 spill_14 (uint32_t *in, uint32_t *out)
247 {
248 register vuint32m8_t v8 asm("v8") = *(vuint32m8_t*)in;
249 asm volatile ("# %0"::"vr"(v8));
250 exhaust_vector_regs ();
251 register vuint32m8_t v16 asm("v16") = v8;
252 *(vuint32m8_t*)out = v16;
253 asm volatile ("# %0"::"vr"(v16));
254 }