1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
3 /* { dg-final { check-function-bodies "**" "" } } */
4
5 #include "riscv_vector.h"
6 #include "macro.h"
7
8 /*
9 ** spill_2:
10 ** csrr\tt0,vlenb
11 ** sub\tsp,sp,t0
12 ** vsetvli\ta5,zero,e16,mf4,ta,ma
13 ** vle16.v\tv[0-9]+,0\(a0\)
14 ** csrr\t[a-x0-9]+,vlenb
15 ** srli\t[a-x0-9]+,[a-x0-9]+,2
16 ** slli\t[a-x0-9]+,[a-x0-9]+,2
17 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
18 ** add\t[a-x0-9]+,[a-x0-9]+,sp
19 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
20 ** ...
21 ** csrr\t[a-x0-9]+,vlenb
22 ** srli\t[a-x0-9]+,[a-x0-9]+,2
23 ** slli\t[a-x0-9]+,[a-x0-9]+,2
24 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
25 ** add\t[a-x0-9]+,[a-x0-9]+,sp
26 ** vle16.v\tv[0-9]+,0\([a-x0-9]+\)
27 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
28 ** csrr\tt0,vlenb
29 ** add\tsp,sp,t0
30 ** ...
31 ** jr\tra
32 */
33 void
34 spill_2 (int16_t *in, int16_t *out)
35 {
36 vint16mf4_t v1 = *(vint16mf4_t*)in;
37 exhaust_vector_regs ();
38 *(vint16mf4_t*)out = v1;
39 }
40
41 /*
42 ** spill_3:
43 ** csrr\tt0,vlenb
44 ** sub\tsp,sp,t0
45 ** vsetvli\ta5,zero,e16,mf2,ta,ma
46 ** vle16.v\tv[0-9]+,0\(a0\)
47 ** csrr\t[a-x0-9]+,vlenb
48 ** srli\t[a-x0-9]+,[a-x0-9]+,1
49 ** add\t[a-x0-9]+,[a-x0-9]+,sp
50 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
51 ** ...
52 ** csrr\t[a-x0-9]+,vlenb
53 ** srli\t[a-x0-9]+,[a-x0-9]+,1
54 ** add\t[a-x0-9]+,[a-x0-9]+,sp
55 ** vle16.v\tv[0-9]+,0\([a-x0-9]+\)
56 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
57 ** csrr\tt0,vlenb
58 ** add\tsp,sp,t0
59 ** ...
60 ** jr\tra
61 */
62 void
63 spill_3 (int16_t *in, int16_t *out)
64 {
65 vint16mf2_t v1 = *(vint16mf2_t*)in;
66 exhaust_vector_regs ();
67 *(vint16mf2_t*)out = v1;
68 }
69
70 /*
71 ** spill_4:
72 ** csrr\tt0,vlenb
73 ** sub\tsp,sp,t0
74 ** ...
75 ** vs1r.v\tv[0-9]+,0\(sp\)
76 ** ...
77 ** vl1re16.v\tv2,0\(sp\)
78 ** vs1r.v\tv2,0\([a-x0-9]+\)
79 ** ...
80 ** jr\tra
81 */
82 void
83 spill_4 (int16_t *in, int16_t *out)
84 {
85 register vint16m1_t v1 asm("v1") = *(vint16m1_t*)in;
86 asm volatile ("# %0"::"vr"(v1));
87 exhaust_vector_regs ();
88 register vint16m1_t v2 asm("v2") = v1;
89 *(vint16m1_t*)out = v2;
90 asm volatile ("# %0"::"vr"(v2));
91 }
92
93 /*
94 ** spill_5:
95 ** csrr\tt0,vlenb
96 ** slli\tt1,t0,1
97 ** sub\tsp,sp,t1
98 ** ...
99 ** vs2r.v\tv[0-9]+,0\(sp\)
100 ** ...
101 ** vl2re16.v\tv4,0\(sp\)
102 ** vs2r.v\tv4,0\([a-x0-9]+\)
103 ** ...
104 ** jr\tra
105 */
106 void
107 spill_5 (int16_t *in, int16_t *out)
108 {
109 register vint16m2_t v2 asm("v2") = *(vint16m2_t*)in;
110 asm volatile ("# %0"::"vr"(v2));
111 exhaust_vector_regs ();
112 register vint16m2_t v4 asm("v4") = v2;
113 *(vint16m2_t*)out = v4;
114 asm volatile ("# %0"::"vr"(v4));
115 }
116
117 /*
118 ** spill_6:
119 ** csrr\tt0,vlenb
120 ** slli\tt1,t0,2
121 ** sub\tsp,sp,t1
122 ** ...
123 ** vs4r.v\tv[0-9]+,0\(sp\)
124 ** ...
125 ** vl4re16.v\tv8,0\(sp\)
126 ** vs4r.v\tv8,0\([a-x0-9]+\)
127 ** ...
128 ** jr\tra
129 */
130 void
131 spill_6 (int16_t *in, int16_t *out)
132 {
133 register vint16m4_t v4 asm("v4") = *(vint16m4_t*)in;
134 asm volatile ("# %0"::"vr"(v4));
135 exhaust_vector_regs ();
136 register vint16m4_t v8 asm("v8") = v4;
137 *(vint16m4_t*)out = v8;
138 asm volatile ("# %0"::"vr"(v8));
139 }
140
141 /*
142 ** spill_7:
143 ** csrr\tt0,vlenb
144 ** slli\tt1,t0,3
145 ** sub\tsp,sp,t1
146 ** ...
147 ** vs8r.v\tv[0-9]+,0\(sp\)
148 ** ...
149 ** vl8re16.v\tv16,0\(sp\)
150 ** vs8r.v\tv16,0\([a-x0-9]+\)
151 ** ...
152 ** jr\tra
153 */
154 void
155 spill_7 (int16_t *in, int16_t *out)
156 {
157 register vint16m8_t v8 asm("v8") = *(vint16m8_t*)in;
158 asm volatile ("# %0"::"vr"(v8));
159 exhaust_vector_regs ();
160 register vint16m8_t v16 asm("v16") = v8;
161 *(vint16m8_t*)out = v16;
162 asm volatile ("# %0"::"vr"(v16));
163 }
164
165 /*
166 ** spill_9:
167 ** csrr\tt0,vlenb
168 ** sub\tsp,sp,t0
169 ** vsetvli\ta5,zero,e16,mf4,ta,ma
170 ** vle16.v\tv[0-9]+,0\(a0\)
171 ** csrr\t[a-x0-9]+,vlenb
172 ** srli\t[a-x0-9]+,[a-x0-9]+,2
173 ** slli\t[a-x0-9]+,[a-x0-9]+,2
174 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
175 ** add\t[a-x0-9]+,[a-x0-9]+,sp
176 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
177 ** ...
178 ** csrr\t[a-x0-9]+,vlenb
179 ** srli\t[a-x0-9]+,[a-x0-9]+,2
180 ** slli\t[a-x0-9]+,[a-x0-9]+,2
181 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
182 ** add\t[a-x0-9]+,[a-x0-9]+,sp
183 ** vle16.v\tv[0-9]+,0\([a-x0-9]+\)
184 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
185 ** csrr\tt0,vlenb
186 ** add\tsp,sp,t0
187 ** ...
188 ** jr\tra
189 */
190 void
191 spill_9 (uint16_t *in, uint16_t *out)
192 {
193 vuint16mf4_t v1 = *(vuint16mf4_t*)in;
194 exhaust_vector_regs ();
195 *(vuint16mf4_t*)out = v1;
196 }
197
198 /*
199 ** spill_10:
200 ** csrr\tt0,vlenb
201 ** sub\tsp,sp,t0
202 ** vsetvli\ta5,zero,e16,mf2,ta,ma
203 ** vle16.v\tv[0-9]+,0\(a0\)
204 ** csrr\t[a-x0-9]+,vlenb
205 ** srli\t[a-x0-9]+,[a-x0-9]+,1
206 ** add\t[a-x0-9]+,[a-x0-9]+,sp
207 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
208 ** ...
209 ** csrr\t[a-x0-9]+,vlenb
210 ** srli\t[a-x0-9]+,[a-x0-9]+,1
211 ** add\t[a-x0-9]+,[a-x0-9]+,sp
212 ** vle16.v\tv[0-9]+,0\([a-x0-9]+\)
213 ** vse16.v\tv[0-9]+,0\([a-x0-9]+\)
214 ** csrr\tt0,vlenb
215 ** add\tsp,sp,t0
216 ** ...
217 ** jr\tra
218 */
219 void
220 spill_10 (uint16_t *in, uint16_t *out)
221 {
222 vuint16mf2_t v1 = *(vuint16mf2_t*)in;
223 exhaust_vector_regs ();
224 *(vuint16mf2_t*)out = v1;
225 }
226
227 /*
228 ** spill_11:
229 ** csrr\tt0,vlenb
230 ** sub\tsp,sp,t0
231 ** ...
232 ** vs1r.v\tv[0-9]+,0\(sp\)
233 ** ...
234 ** vl1re16.v\tv2,0\(sp\)
235 ** vs1r.v\tv2,0\([a-x0-9]+\)
236 ** ...
237 ** jr\tra
238 */
239 void
240 spill_11 (uint16_t *in, uint16_t *out)
241 {
242 register vuint16m1_t v1 asm("v1") = *(vuint16m1_t*)in;
243 asm volatile ("# %0"::"vr"(v1));
244 exhaust_vector_regs ();
245 register vuint16m1_t v2 asm("v2") = v1;
246 *(vuint16m1_t*)out = v2;
247 asm volatile ("# %0"::"vr"(v2));
248 }
249
250 /*
251 ** spill_12:
252 ** csrr\tt0,vlenb
253 ** slli\tt1,t0,1
254 ** sub\tsp,sp,t1
255 ** ...
256 ** vs2r.v\tv[0-9]+,0\(sp\)
257 ** ...
258 ** vl2re16.v\tv4,0\(sp\)
259 ** vs2r.v\tv4,0\([a-x0-9]+\)
260 ** ...
261 ** jr\tra
262 */
263 void
264 spill_12 (uint16_t *in, uint16_t *out)
265 {
266 register vuint16m2_t v2 asm("v2") = *(vuint16m2_t*)in;
267 asm volatile ("# %0"::"vr"(v2));
268 exhaust_vector_regs ();
269 register vuint16m2_t v4 asm("v4") = v2;
270 *(vuint16m2_t*)out = v4;
271 asm volatile ("# %0"::"vr"(v4));
272 }
273
274 /*
275 ** spill_13:
276 ** csrr\tt0,vlenb
277 ** slli\tt1,t0,2
278 ** sub\tsp,sp,t1
279 ** ...
280 ** vs4r.v\tv[0-9]+,0\(sp\)
281 ** ...
282 ** vl4re16.v\tv8,0\(sp\)
283 ** vs4r.v\tv8,0\([a-x0-9]+\)
284 ** ...
285 ** jr\tra
286 */
287 void
288 spill_13 (uint16_t *in, uint16_t *out)
289 {
290 register vuint16m4_t v4 asm("v4") = *(vuint16m4_t*)in;
291 asm volatile ("# %0"::"vr"(v4));
292 exhaust_vector_regs ();
293 register vuint16m4_t v8 asm("v8") = v4;
294 *(vuint16m4_t*)out = v8;
295 asm volatile ("# %0"::"vr"(v8));
296 }
297
298 /*
299 ** spill_14:
300 ** csrr\tt0,vlenb
301 ** slli\tt1,t0,3
302 ** sub\tsp,sp,t1
303 ** ...
304 ** vs8r.v\tv[0-9]+,0\(sp\)
305 ** ...
306 ** vl8re16.v\tv16,0\(sp\)
307 ** vs8r.v\tv16,0\([a-x0-9]+\)
308 ** ...
309 ** jr\tra
310 */
311 void
312 spill_14 (uint16_t *in, uint16_t *out)
313 {
314 register vuint16m8_t v8 asm("v8") = *(vuint16m8_t*)in;
315 asm volatile ("# %0"::"vr"(v8));
316 exhaust_vector_regs ();
317 register vuint16m8_t v16 asm("v16") = v8;
318 *(vuint16m8_t*)out = v16;
319 asm volatile ("# %0"::"vr"(v16));
320 }