(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
riscv/
rvv/
base/
spill-10.c
       1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -fno-schedule-insns -fno-schedule-insns2 -O3" } */
       3  /* { dg-final { check-function-bodies "**" "" } } */
       4  
       5  #include "riscv_vector.h"
       6  
       7  void f (char*);
       8  
       9  /*
      10  ** stach_check_alloca_1:
      11  **	addi\tsp,sp,-32
      12  **	sw\tra,4\(sp\)
      13  **	sw\ts0,0\(sp\)
      14  **	addi\ts0,sp,8
      15  **	csrr\tt0,vlenb
      16  **	sub\tsp,sp,t0
      17  **	...
      18  **	addi\ta2,a2,15
      19  **	andi\ta2,a2,-8
      20  **	sub\tsp,sp,a2
      21  **	...
      22  **	lw\tra,4\(sp\)
      23  **	lw\ts0,0\(sp\)
      24  **	addi\tsp,sp,32
      25  **	jr\tra
      26  */
      27  void stach_check_alloca_1 (vuint8m1_t data, uint8_t *base, int y, ...)
      28  {
      29    vuint8m8_t v0, v8, v16, v24;
      30    asm volatile ("nop"
      31                  : "=vr" (v0), "=vr" (v8), "=vr" (v16), "=vr" (v24)
      32                  :
      33                  :);
      34    asm volatile ("nop"
      35                  :
      36                  : "vr" (v0), "vr" (v8), "vr" (v16), "vr" (v24)
      37                  :);
      38    *(vuint8m1_t *)base = data;
      39    char* pStr = (char*)__builtin_alloca(y);
      40    f(pStr);
      41  }