1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gcv -mabi=ilp32 -mpreferred-stack-boundary=3 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
3 /* { dg-final { check-function-bodies "**" "" } } */
4
5 #include "riscv_vector.h"
6 #include "macro.h"
7
8 /*
9 ** spill_1:
10 ** csrr\tt0,vlenb
11 ** sub\tsp,sp,t0
12 ** ...
13 ** csrr\t[a-x0-9]+,vlenb
14 ** srli\t[a-x0-9]+,[a-x0-9]+,3
15 ** slli\t[a-x0-9]+,[a-x0-9]+,3
16 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
17 ** add\t[a-x0-9]+,[a-x0-9]+,sp
18 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
19 ** ...
20 ** csrr\t[a-x0-9]+,vlenb
21 ** srli\t[a-x0-9]+,[a-x0-9]+,3
22 ** slli\t[a-x0-9]+,[a-x0-9]+,3
23 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
24 ** add\t[a-x0-9]+,[a-x0-9]+,sp
25 ** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
26 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
27 ** csrr\tt0,vlenb
28 ** add\tsp,sp,t0
29 ** ...
30 ** jr\tra
31 */
32 void
33 spill_1 (int8_t *in, int8_t *out)
34 {
35 vint8mf8_t v1 = *(vint8mf8_t*)in;
36 exhaust_vector_regs ();
37 *(vint8mf8_t*)out = v1;
38 }
39
40 /*
41 ** spill_2:
42 ** csrr\tt0,vlenb
43 ** sub\tsp,sp,t0
44 ** vsetvli\ta5,zero,e8,mf4,ta,ma
45 ** vle8.v\tv[0-9]+,0\(a0\)
46 ** csrr\t[a-x0-9]+,vlenb
47 ** srli\t[a-x0-9]+,[a-x0-9]+,2
48 ** slli\t[a-x0-9]+,[a-x0-9]+,2
49 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
50 ** add\t[a-x0-9]+,[a-x0-9]+,sp
51 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
52 ** ...
53 ** csrr\t[a-x0-9]+,vlenb
54 ** srli\t[a-x0-9]+,[a-x0-9]+,2
55 ** slli\t[a-x0-9]+,[a-x0-9]+,2
56 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
57 ** add\t[a-x0-9]+,[a-x0-9]+,sp
58 ** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
59 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
60 ** csrr\tt0,vlenb
61 ** add\tsp,sp,t0
62 ** ...
63 ** jr\tra
64 */
65 void
66 spill_2 (int8_t *in, int8_t *out)
67 {
68 vint8mf4_t v1 = *(vint8mf4_t*)in;
69 exhaust_vector_regs ();
70 *(vint8mf4_t*)out = v1;
71 }
72
73 /*
74 ** spill_3:
75 ** csrr\tt0,vlenb
76 ** sub\tsp,sp,t0
77 ** vsetvli\ta5,zero,e8,mf2,ta,ma
78 ** vle8.v\tv[0-9]+,0\(a0\)
79 ** csrr\t[a-x0-9]+,vlenb
80 ** srli\t[a-x0-9]+,[a-x0-9]+,1
81 ** add\t[a-x0-9]+,[a-x0-9]+,sp
82 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
83 ** ...
84 ** csrr\t[a-x0-9]+,vlenb
85 ** srli\t[a-x0-9]+,[a-x0-9]+,1
86 ** add\t[a-x0-9]+,[a-x0-9]+,sp
87 ** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
88 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
89 ** csrr\tt0,vlenb
90 ** add\tsp,sp,t0
91 ** ...
92 ** jr\tra
93 */
94 void
95 spill_3 (int8_t *in, int8_t *out)
96 {
97 vint8mf2_t v1 = *(vint8mf2_t*)in;
98 exhaust_vector_regs ();
99 *(vint8mf2_t*)out = v1;
100 }
101
102 /*
103 ** spill_4:
104 ** csrr\tt0,vlenb
105 ** sub\tsp,sp,t0
106 ** ...
107 ** vs1r.v\tv[0-9]+,0\(sp\)
108 ** ...
109 ** vl1re8.v\tv2,0\(sp\)
110 ** vs1r.v\tv2,0\([a-x0-9]+\)
111 ** ...
112 ** jr\tra
113 */
114 void
115 spill_4 (int8_t *in, int8_t *out)
116 {
117 register vint8m1_t v1 asm("v1") = *(vint8m1_t*)in;
118 asm volatile ("# %0"::"vr"(v1));
119 exhaust_vector_regs ();
120 register vint8m1_t v2 asm("v2") = v1;
121 *(vint8m1_t*)out = v2;
122 asm volatile ("# %0"::"vr"(v2));
123 }
124
125 /*
126 ** spill_5:
127 ** csrr\tt0,vlenb
128 ** slli\tt1,t0,1
129 ** sub\tsp,sp,t1
130 ** ...
131 ** vs2r.v\tv[0-9]+,0\(sp\)
132 ** ...
133 ** vl2re8.v\tv4,0\(sp\)
134 ** vs2r.v\tv4,0\([a-x0-9]+\)
135 ** ...
136 ** jr\tra
137 */
138 void
139 spill_5 (int8_t *in, int8_t *out)
140 {
141 register vint8m2_t v2 asm("v2") = *(vint8m2_t*)in;
142 asm volatile ("# %0"::"vr"(v2));
143 exhaust_vector_regs ();
144 register vint8m2_t v4 asm("v4") = v2;
145 *(vint8m2_t*)out = v4;
146 asm volatile ("# %0"::"vr"(v4));
147 }
148
149 /*
150 ** spill_6:
151 ** csrr\tt0,vlenb
152 ** slli\tt1,t0,2
153 ** sub\tsp,sp,t1
154 ** ...
155 ** vs4r.v\tv[0-9]+,0\(sp\)
156 ** ...
157 ** vl4re8.v\tv8,0\(sp\)
158 ** vs4r.v\tv8,0\([a-x0-9]+\)
159 ** ...
160 ** jr\tra
161 */
162 void
163 spill_6 (int8_t *in, int8_t *out)
164 {
165 register vint8m4_t v4 asm("v4") = *(vint8m4_t*)in;
166 asm volatile ("# %0"::"vr"(v4));
167 exhaust_vector_regs ();
168 register vint8m4_t v8 asm("v8") = v4;
169 *(vint8m4_t*)out = v8;
170 asm volatile ("# %0"::"vr"(v8));
171 }
172
173 /*
174 ** spill_7:
175 ** csrr\tt0,vlenb
176 ** slli\tt1,t0,3
177 ** sub\tsp,sp,t1
178 ** ...
179 ** vs8r.v\tv[0-9]+,0\(sp\)
180 ** ...
181 ** vl8re8.v\tv16,0\(sp\)
182 ** vs8r.v\tv16,0\([a-x0-9]+\)
183 ** ...
184 ** jr\tra
185 */
186 void
187 spill_7 (int8_t *in, int8_t *out)
188 {
189 register vint8m8_t v8 asm("v8") = *(vint8m8_t*)in;
190 asm volatile ("# %0"::"vr"(v8));
191 exhaust_vector_regs ();
192 register vint8m8_t v16 asm("v16") = v8;
193 *(vint8m8_t*)out = v16;
194 asm volatile ("# %0"::"vr"(v16));
195 }
196
197 /*
198 ** spill_8:
199 ** csrr\tt0,vlenb
200 ** sub\tsp,sp,t0
201 ** vsetvli\ta5,zero,e8,mf8,ta,ma
202 ** vle8.v\tv[0-9]+,0\(a0\)
203 ** csrr\t[a-x0-9]+,vlenb
204 ** srli\t[a-x0-9]+,[a-x0-9]+,3
205 ** slli\t[a-x0-9]+,[a-x0-9]+,3
206 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
207 ** add\t[a-x0-9]+,[a-x0-9]+,sp
208 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
209 ** ...
210 ** csrr\t[a-x0-9]+,vlenb
211 ** srli\t[a-x0-9]+,[a-x0-9]+,3
212 ** slli\t[a-x0-9]+,[a-x0-9]+,3
213 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
214 ** add\t[a-x0-9]+,[a-x0-9]+,sp
215 ** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
216 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
217 ** csrr\tt0,vlenb
218 ** add\tsp,sp,t0
219 ** ...
220 ** jr\tra
221 */
222 void
223 spill_8 (uint8_t *in, uint8_t *out)
224 {
225 vuint8mf8_t v1 = *(vuint8mf8_t*)in;
226 exhaust_vector_regs ();
227 *(vuint8mf8_t*)out = v1;
228 }
229
230 /*
231 ** spill_9:
232 ** csrr\tt0,vlenb
233 ** sub\tsp,sp,t0
234 ** vsetvli\ta5,zero,e8,mf4,ta,ma
235 ** vle8.v\tv[0-9]+,0\(a0\)
236 ** csrr\t[a-x0-9]+,vlenb
237 ** srli\t[a-x0-9]+,[a-x0-9]+,2
238 ** slli\t[a-x0-9]+,[a-x0-9]+,2
239 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
240 ** add\t[a-x0-9]+,[a-x0-9]+,sp
241 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
242 ** ...
243 ** csrr\t[a-x0-9]+,vlenb
244 ** srli\t[a-x0-9]+,[a-x0-9]+,2
245 ** slli\t[a-x0-9]+,[a-x0-9]+,2
246 ** sub\t[a-x0-9]+,[a-x0-9]+,[a-x0-9]+
247 ** add\t[a-x0-9]+,[a-x0-9]+,sp
248 ** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
249 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
250 ** csrr\tt0,vlenb
251 ** add\tsp,sp,t0
252 ** ...
253 ** jr\tra
254 */
255 void
256 spill_9 (uint8_t *in, uint8_t *out)
257 {
258 vuint8mf4_t v1 = *(vuint8mf4_t*)in;
259 exhaust_vector_regs ();
260 *(vuint8mf4_t*)out = v1;
261 }
262
263 /*
264 ** spill_10:
265 ** csrr\tt0,vlenb
266 ** sub\tsp,sp,t0
267 ** vsetvli\ta5,zero,e8,mf2,ta,ma
268 ** vle8.v\tv[0-9]+,0\(a0\)
269 ** csrr\t[a-x0-9]+,vlenb
270 ** srli\t[a-x0-9]+,[a-x0-9]+,1
271 ** add\t[a-x0-9]+,[a-x0-9]+,sp
272 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
273 ** ...
274 ** csrr\t[a-x0-9]+,vlenb
275 ** srli\t[a-x0-9]+,[a-x0-9]+,1
276 ** add\t[a-x0-9]+,[a-x0-9]+,sp
277 ** vle8.v\tv[0-9]+,0\([a-x0-9]+\)
278 ** vse8.v\tv[0-9]+,0\([a-x0-9]+\)
279 ** csrr\tt0,vlenb
280 ** add\tsp,sp,t0
281 ** ...
282 ** jr\tra
283 */
284 void
285 spill_10 (uint8_t *in, uint8_t *out)
286 {
287 vuint8mf2_t v1 = *(vuint8mf2_t*)in;
288 exhaust_vector_regs ();
289 *(vuint8mf2_t*)out = v1;
290 }
291
292 /*
293 ** spill_11:
294 ** csrr\tt0,vlenb
295 ** sub\tsp,sp,t0
296 ** ...
297 ** vs1r.v\tv[0-9]+,0\(sp\)
298 ** ...
299 ** vl1re8.v\tv2,0\(sp\)
300 ** vs1r.v\tv2,0\([a-x0-9]+\)
301 ** ...
302 ** jr\tra
303 */
304 void
305 spill_11 (uint8_t *in, uint8_t *out)
306 {
307 register vuint8m1_t v1 asm("v1") = *(vuint8m1_t*)in;
308 asm volatile ("# %0"::"vr"(v1));
309 exhaust_vector_regs ();
310 register vuint8m1_t v2 asm("v2") = v1;
311 *(vuint8m1_t*)out = v2;
312 asm volatile ("# %0"::"vr"(v2));
313 }
314
315 /*
316 ** spill_12:
317 ** csrr\tt0,vlenb
318 ** slli\tt1,t0,1
319 ** sub\tsp,sp,t1
320 ** ...
321 ** vs2r.v\tv[0-9]+,0\(sp\)
322 ** ...
323 ** vl2re8.v\tv4,0\(sp\)
324 ** vs2r.v\tv4,0\([a-x0-9]+\)
325 ** ...
326 ** jr\tra
327 */
328 void
329 spill_12 (uint8_t *in, uint8_t *out)
330 {
331 register vuint8m2_t v2 asm("v2") = *(vuint8m2_t*)in;
332 asm volatile ("# %0"::"vr"(v2));
333 exhaust_vector_regs ();
334 register vuint8m2_t v4 asm("v4") = v2;
335 *(vuint8m2_t*)out = v4;
336 asm volatile ("# %0"::"vr"(v4));
337 }
338
339 /*
340 ** spill_13:
341 ** csrr\tt0,vlenb
342 ** slli\tt1,t0,2
343 ** sub\tsp,sp,t1
344 ** ...
345 ** vs4r.v\tv[0-9]+,0\(sp\)
346 ** ...
347 ** vl4re8.v\tv8,0\(sp\)
348 ** vs4r.v\tv8,0\([a-x0-9]+\)
349 ** ...
350 ** jr\tra
351 */
352 void
353 spill_13 (uint8_t *in, uint8_t *out)
354 {
355 register vuint8m4_t v4 asm("v4") = *(vuint8m4_t*)in;
356 asm volatile ("# %0"::"vr"(v4));
357 exhaust_vector_regs ();
358 register vuint8m4_t v8 asm("v8") = v4;
359 *(vuint8m4_t*)out = v8;
360 asm volatile ("# %0"::"vr"(v8));
361 }
362
363 /*
364 ** spill_14:
365 ** csrr\tt0,vlenb
366 ** slli\tt1,t0,3
367 ** sub\tsp,sp,t1
368 ** ...
369 ** vs8r.v\tv[0-9]+,0\(sp\)
370 ** ...
371 ** vl8re8.v\tv16,0\(sp\)
372 ** vs8r.v\tv16,0\([a-x0-9]+\)
373 ** ...
374 ** jr\tra
375 */
376 void
377 spill_14 (uint8_t *in, uint8_t *out)
378 {
379 register vuint8m8_t v8 asm("v8") = *(vuint8m8_t*)in;
380 asm volatile ("# %0"::"vr"(v8));
381 exhaust_vector_regs ();
382 register vuint8m8_t v16 asm("v16") = v8;
383 *(vuint8m8_t*)out = v16;
384 asm volatile ("# %0"::"vr"(v16));
385 }