1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32d -fno-schedule-insns -fno-schedule-insns2 -O3" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  vuint64m2_t f1(vuint64m2_t var_17, uint64_t var_60)
       7  {
       8    vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 0);
       9    return var_16;
      10  }
      11  
      12  vuint64m2_t f2(vuint64m2_t var_17, uint64_t var_60)
      13  {
      14    vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, 4);
      15    return var_16;
      16  }
      17  
      18  vuint64m2_t f3(vuint64m2_t var_17, uint64_t var_60, size_t vl)
      19  {
      20    vuint64m2_t var_16 = __riscv_vmv_s_x_u64m2_tu(var_17,var_60, vl);
      21    return var_16;
      22  }
      23  
      24  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*0,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */
      25  /* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*1,\s*e64,\s*m2,\s*t[au],\s*m[au]} 1 } } */
      26  /* { dg-final { scan-assembler-times {sgtu} 1 } } */