1 /* { dg-do compile } */
2 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
3
4 #include "riscv_vector.h"
5
6 void f0 (void *base,void *out,size_t vl)
7 {
8 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base, vl);
9 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2(src,vl);
10 __riscv_vse32_v_f32mf2 (out,v,vl);
11 }
12
13 void f1 (void *base,void *out,size_t vl)
14 {
15 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base, vl);
16 vfloat32mf2_t src2 = __riscv_vle32_v_f32mf2 ((void *)(base + 100), vl);
17 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2_tu(src2,src,vl);
18 __riscv_vse32_v_f32mf2 (out,v,vl);
19 }
20
21 void f2 (void *base,void *out,size_t vl)
22 {
23 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base, vl);
24 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2(src,vl);
25 vfloat64m1_t v2 = __riscv_vfadd_vv_f64m1 (src, src,vl);
26 __riscv_vse32_v_f32mf2 (out,v,vl);
27 __riscv_vse64_v_f64m1 ((void *)out,v2,vl);
28 }
29
30 void f3 (void *base,void *out,size_t vl, int n)
31 {
32 for (int i = 0; i < n; i++){
33 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base + 100*i, vl);
34 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2(src,vl);
35 vfloat64m1_t v2 = __riscv_vfadd_vv_f64m1 (src, src,vl);
36 __riscv_vse32_v_f32mf2 (out + 100*i,v,vl);
37 __riscv_vse64_v_f64m1 ((void *)(out + 200*i),v2,vl);
38 }
39 }
40
41 void f4 (void *base,void *out,size_t vl)
42 {
43 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base, vl);
44 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2(src,vl);
45 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
46 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
47 vfloat64m1_t v2 = __riscv_vfadd_vv_f64m1 (src, src,vl);
48 __riscv_vse32_v_f32mf2 (out,v,vl);
49 __riscv_vse64_v_f64m1 ((void *)out,v2,vl);
50 }
51
52 void f5 (void *base,void *base2,void *out,size_t vl, int n)
53 {
54 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base + 100, vl);
55 for (int i = 0; i < n; i++){
56 vbool64_t m = __riscv_vlm_v_b64 (base + i, vl);
57 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2_m(m,src,vl);
58 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
59 v = __riscv_vle32_v_f32mf2_tu (v, base2, vl);
60 __riscv_vse32_v_f32mf2 (out + 100*i,v,vl);
61 }
62 }
63
64 void f6 (void *base,void *out,size_t vl)
65 {
66 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base, vl);
67 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1(src,vl);
68 __riscv_vse32_v_f32m1 (out,v,vl);
69 }
70
71 void f7 (void *base,void *out,size_t vl)
72 {
73 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base, vl);
74 vfloat32m1_t src2 = __riscv_vle32_v_f32m1 ((void *)(base + 100), vl);
75 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(src2,src,vl);
76 __riscv_vse32_v_f32m1 (out,v,vl);
77 }
78
79 void f8 (void *base,void *out,size_t vl)
80 {
81 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base, vl);
82 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1(src,vl);
83 vfloat64m2_t v2 = __riscv_vfadd_vv_f64m2 (src, src,vl);
84 __riscv_vse32_v_f32m1 (out,v,vl);
85 __riscv_vse64_v_f64m2 ((void *)out,v2,vl);
86 }
87
88 void f9 (void *base,void *out,size_t vl, int n)
89 {
90 for (int i = 0; i < n; i++){
91 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base + 100*i, vl);
92 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1(src,vl);
93 vfloat64m2_t v2 = __riscv_vfadd_vv_f64m2 (src, src,vl);
94 __riscv_vse32_v_f32m1 (out + 100*i,v,vl);
95 __riscv_vse64_v_f64m2 ((void *)(out + 200*i),v2,vl);
96 }
97 }
98
99 void f10 (void *base,void *out,size_t vl)
100 {
101 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base, vl);
102 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1(src,vl);
103 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
104 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
105 vfloat64m2_t v2 = __riscv_vfadd_vv_f64m2 (src, src,vl);
106 __riscv_vse32_v_f32m1 (out,v,vl);
107 __riscv_vse64_v_f64m2 ((void *)out,v2,vl);
108 }
109
110 void f11 (void *base,void *base2,void *out,size_t vl, int n)
111 {
112 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base + 100, vl);
113 for (int i = 0; i < n; i++){
114 vbool32_t m = __riscv_vlm_v_b32 (base + i, vl);
115 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1_m(m,src,vl);
116 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
117 v = __riscv_vle32_v_f32m1_tu (v, base2, vl);
118 __riscv_vse32_v_f32m1 (out + 100*i,v,vl);
119 }
120 }
121
122 void f12 (void *base,void *out,size_t vl, int n)
123 {
124 vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((void *)(base + 1000), vl);
125 for (int i = 0; i < n; i++){
126 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base + 100*i, vl);
127 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
128 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
129 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
130 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
131 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
132 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
133 __riscv_vse32_v_f32mf2 (out + 100*i,v,vl);
134 }
135 }
136
137 void f13 (void *base,void *out,size_t vl, int n)
138 {
139 vfloat32m1_t v = __riscv_vle32_v_f32m1 ((void *)(base + 1000), vl);
140 for (int i = 0; i < n; i++){
141 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base + 100*i, vl);
142 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
143 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
144 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
145 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
146 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
147 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
148 __riscv_vse32_v_f32m1 (out + 100*i,v,vl);
149 }
150 }
151
152 void f14 (void *base,void *out,size_t vl, int n)
153 {
154 for (int i = 0; i < n; i++){
155 vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((void *)(base + 1000 * i), vl);
156 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base + 100*i, vl);
157 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
158 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
159 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
160 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
161 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
162 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src,vl);
163 __riscv_vse32_v_f32mf2 (out + 100*i,v,vl);
164 }
165 }
166
167 void f15 (void *base,void *out,size_t vl, int n)
168 {
169 for (int i = 0; i < n; i++){
170 vfloat32m1_t v = __riscv_vle32_v_f32m1 ((void *)(base + 1000 * i), vl);
171 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base + 100*i, vl);
172 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
173 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
174 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
175 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
176 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
177 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src,vl);
178 __riscv_vse32_v_f32m1 (out + 100*i,v,vl);
179 }
180 }
181
182 void f16 (void *base,void *out,size_t vl, int n)
183 {
184 for (int i = 0; i < n; i++){
185 vfloat32mf2_t v = __riscv_vle32_v_f32mf2 ((void *)(base + 1000 * i), vl);
186 vfloat64m1_t src1 = __riscv_vle64_v_f64m1 (base + 100*i, vl);
187 vfloat64m1_t src2 = __riscv_vle64_v_f64m1 (base + 200*i, vl);
188 vfloat64m1_t src3 = __riscv_vle64_v_f64m1 (base + 300*i, vl);
189 vfloat64m1_t src4 = __riscv_vle64_v_f64m1 (base + 400*i, vl);
190 vfloat64m1_t src5 = __riscv_vle64_v_f64m1 (base + 500*i, vl);
191 vfloat64m1_t src6 = __riscv_vle64_v_f64m1 (base + 600*i, vl);
192 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src1,vl);
193 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src2,vl);
194 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src3,vl);
195 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src4,vl);
196 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src5,vl);
197 v = __riscv_vfncvt_f_f_w_f32mf2_tu(v,src6,vl);
198 __riscv_vse32_v_f32mf2 (out + 100*i,v,vl);
199 }
200 }
201
202 void f17 (void *base,void *out,size_t vl, int n)
203 {
204 for (int i = 0; i < n; i++){
205 vfloat32m1_t v = __riscv_vle32_v_f32m1 ((void *)(base + 1000 * i), vl);
206 vfloat64m2_t src1 = __riscv_vle64_v_f64m2 (base + 100*i, vl);
207 vfloat64m2_t src2 = __riscv_vle64_v_f64m2 (base + 200*i, vl);
208 vfloat64m2_t src3 = __riscv_vle64_v_f64m2 (base + 300*i, vl);
209 vfloat64m2_t src4 = __riscv_vle64_v_f64m2 (base + 400*i, vl);
210 vfloat64m2_t src5 = __riscv_vle64_v_f64m2 (base + 500*i, vl);
211 vfloat64m2_t src6 = __riscv_vle64_v_f64m2 (base + 600*i, vl);
212 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src1,vl);
213 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src2,vl);
214 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src3,vl);
215 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src4,vl);
216 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src5,vl);
217 v = __riscv_vfncvt_rod_f_f_w_f32m1_tu(v,src6,vl);
218 __riscv_vse32_v_f32m1 (out + 100*i,v,vl);
219 }
220 }
221
222 void f18 (void *base,void *out,size_t vl)
223 {
224 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base, vl);
225 /* Only allow load v30,v31. */
226 asm volatile("#" ::
227 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
228 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
229 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
230 "v26", "v27", "v28", "v29");
231
232 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1(src,vl);
233 /* Only allow vncvt SRC == DEST v30. */
234 asm volatile("#" ::
235 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
236 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
237 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
238 "v26", "v27", "v28", "v29", "v31");
239
240 __riscv_vse32_v_f32m1 (out,v,vl);
241 }
242
243 void f19 (void *base,void *out,size_t vl)
244 {
245 vfloat64m1_t src = __riscv_vle64_v_f64m1 (base, vl);
246 /* Only allow load v31. */
247 asm volatile("#" ::
248 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
249 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
250 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
251 "v26", "v27", "v28", "v29", "v30");
252
253 vfloat32mf2_t v = __riscv_vfncvt_f_f_w_f32mf2(src,vl);
254 /* Only allow vncvt SRC == DEST v31. */
255 asm volatile("#" ::
256 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
257 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
258 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
259 "v26", "v27", "v28", "v29", "v30");
260
261 __riscv_vse32_v_f32mf2 (out,v,vl);
262 }
263
264 void f20 (void *base,void *out,size_t vl)
265 {
266 vfloat64m2_t src = __riscv_vle64_v_f64m2 (base, vl);
267 /* Only allow load v30,v31. */
268 asm volatile("#" ::
269 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
270 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
271 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
272 "v26", "v27", "v28", "v29");
273
274 vfloat32m1_t v = __riscv_vfncvt_rod_f_f_w_f32m1(src,vl);
275 /* Only allow v29. */
276 asm volatile("#" ::
277 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
278 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
279 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
280 "v26", "v27", "v28", "v30", "v31");
281 v = __riscv_vfadd_vv_f32m1 (v,v,vl);
282 /* Only allow v29. */
283 asm volatile("#" ::
284 : "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
285 "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17",
286 "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",
287 "v26", "v27", "v28", "v30", "v31");
288
289 __riscv_vse32_v_f32m1 (out,v,vl);
290 }
291
292 /* { dg-final { scan-assembler-not {vmv} } } */
293 /* { dg-final { scan-assembler-not {csrr} } } */