(root)/
gcc-13.2.0/
gcc/
testsuite/
gcc.target/
riscv/
rvv/
base/
merge_constraint-4.c
       1  /* { dg-do compile } */
       2  /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
       3  
       4  #include "riscv_vector.h"
       5  
       6  void f (void *base1,void *base2,void *base3,void *base4,void *out,size_t vl, uint16_t shift)
       7  {
       8      vuint16m1_t v1 = __riscv_vle16_v_u16m1 (base1, vl);
       9      vbool16_t m1 = __riscv_vlm_v_b16 (base3, vl);
      10      vbool16_t m2 = __riscv_vlm_v_b16 (base4, vl);
      11      asm volatile("#" ::
      12  		 : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
      13  		   "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
      14  		   "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
      15  		   "v26", "v27", "v28", "v29");
      16  
      17      vbool16_t v = __riscv_vmsltu_vx_u16m1_b16_mu(m1,m2,v1,shift,vl);
      18      asm volatile("#" ::
      19  		 : "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9",
      20  		   "v10", "v11", "v12", "v13", "v14", "v15", "v16", "v17", 
      21  		   "v18", "v19", "v20", "v21", "v22", "v23", "v24", "v25",  
      22  		   "v26", "v27", "v28", "v29", "v30", "v31");
      23  
      24  
      25      __riscv_vsm_v_b16 (out,v,vl);
      26  }
      27  
      28  /* { dg-final { scan-assembler-times {vmv} 1 } } */