1  /* { dg-options "-O3 -maltivec" } */
       2  /* { dg-require-effective-target powerpc_altivec_ok } */
       3  
       4  /* Check vectorizer can exploit vector rotation instructions on Power, mainly
       5     for the case rotation count isn't const number.
       6  
       7     Check for instructions vrlb/vrlh/vrlw only available if altivec supported. */
       8  
       9  #define N 256
      10  unsigned int suw[N], ruw[N];
      11  unsigned short suh[N], ruh[N];
      12  unsigned char sub[N], rub[N];
      13  extern unsigned char rot_cnt;
      14  
      15  void
      16  testUW ()
      17  {
      18    for (int i = 0; i < 256; ++i)
      19      ruw[i] = (suw[i] >> rot_cnt) | (suw[i] << (sizeof (suw[0]) * 8 - rot_cnt));
      20  }
      21  
      22  void
      23  testUH ()
      24  {
      25    for (int i = 0; i < 256; ++i)
      26      ruh[i] = (unsigned short) (suh[i] >> rot_cnt)
      27  	     | (unsigned short) (suh[i] << (sizeof (suh[0]) * 8 - rot_cnt));
      28  }
      29  
      30  void
      31  testUB ()
      32  {
      33    for (int i = 0; i < 256; ++i)
      34      rub[i] = (unsigned char) (sub[i] >> rot_cnt)
      35  	     | (unsigned char) (sub[i] << (sizeof (sub[0]) * 8 - rot_cnt));
      36  }
      37  
      38  /* { dg-final { scan-assembler {\mvrlw\M} } } */
      39  /* { dg-final { scan-assembler {\mvrlh\M} } } */
      40  /* { dg-final { scan-assembler {\mvrlb\M} } } */