1  /* PR86731.  Verify that the rs6000 gimple-folding code handles the
       2     left shift properly.  */
       3  
       4  /* { dg-do compile } */
       5  /* { dg-require-effective-target powerpc_altivec_ok } */
       6  /* { dg-require-effective-target lp64 } */
       7  /* { dg-options "-maltivec -O3" } */
       8  
       9  #include <altivec.h>
      10  /* The original test as reported.  */
      11  vector unsigned int splat(void)
      12  {
      13          vector unsigned int mzero = vec_splat_u32(-1);
      14          return (vector unsigned int) vec_sl(mzero, mzero);
      15  }
      16  
      17  /* more testcase variations.  */
      18  vector unsigned char splatu1(void)
      19  {
      20          vector unsigned char mzero = vec_splat_u8(-1);
      21          return (vector unsigned char) vec_sl(mzero, mzero);
      22  }
      23  
      24  vector unsigned short splatu2(void)
      25  {
      26          vector unsigned short mzero = vec_splat_u16(-1);
      27          return (vector unsigned short) vec_sl(mzero, mzero);
      28  }
      29  
      30  vector unsigned int splatu3(void)
      31  {
      32          vector unsigned int mzero = vec_splat_u32(-1);
      33          return (vector unsigned int) vec_sl(mzero, mzero);
      34  }
      35  
      36  vector signed char splats1(void)
      37  {
      38          vector unsigned char mzero = vec_splat_u8(-1);
      39          return (vector signed char) vec_sl(mzero, mzero);
      40  }
      41  
      42  vector signed short splats2(void)
      43  {
      44          vector unsigned short mzero = vec_splat_u16(-1);
      45          return (vector signed short) vec_sl(mzero, mzero);
      46  }
      47  
      48  vector signed int splats3(void)
      49  {
      50          vector unsigned int mzero = vec_splat_u32(-1);
      51          return (vector signed int) vec_sl(mzero, mzero);
      52  }
      53  
      54  /* Codegen will consist of splat and shift instructions for most types.
      55     Noted variations:  if gimple folding is disabled, or if -fwrapv is not
      56     specified, the long long tests will generate a vspltisw+vsld pair,
      57     versus generating a single lvx.  */
      58  /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */
      59  /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */
      60  /* { dg-final { scan-assembler-times {\mlvx\M} 0 } } */
      61