1  /* PR86731.  Verify that the rs6000 gimple-folding code handles the
       2     left shift operation properly.  This is a testcase variation that
       3     explicitly specifies -fwrapv, which is a condition for the
       4     gimple folding of the vec_sl() intrinsic.  */
       5  
       6  /* { dg-do compile } */
       7  /* { dg-require-effective-target powerpc_altivec_ok } */
       8  /* { dg-require-effective-target lp64 } */
       9  /* { dg-options "-maltivec -O3 -fwrapv " } */
      10  
      11  #include <altivec.h>
      12  /* original test as reported.  */
      13  vector unsigned int splat(void)
      14  {
      15          vector unsigned int mzero = vec_splat_u32(-1);
      16          return (vector unsigned int) vec_sl(mzero, mzero);
      17  }
      18  
      19  /* more testcase variations.  */
      20  vector unsigned char splatu1(void)
      21  {
      22          vector unsigned char mzero = vec_splat_u8(-1);
      23          return (vector unsigned char) vec_sl(mzero, mzero);
      24  }
      25  
      26  vector unsigned short splatu2(void)
      27  {
      28          vector unsigned short mzero = vec_splat_u16(-1);
      29          return (vector unsigned short) vec_sl(mzero, mzero);
      30  }
      31  
      32  vector unsigned int splatu3(void)
      33  {
      34          vector unsigned int mzero = vec_splat_u32(-1);
      35          return (vector unsigned int) vec_sl(mzero, mzero);
      36  }
      37  
      38  vector signed char splats1(void)
      39  {
      40          vector unsigned char mzero = vec_splat_u8(-1);
      41          return (vector signed char) vec_sl(mzero, mzero);
      42  }
      43  
      44  vector signed short splats2(void)
      45  {
      46          vector unsigned short mzero = vec_splat_u16(-1);
      47          return (vector signed short) vec_sl(mzero, mzero);
      48  }
      49  
      50  vector signed int splats3(void)
      51  {
      52          vector unsigned int mzero = vec_splat_u32(-1);
      53          return (vector signed int) vec_sl(mzero, mzero);
      54  }
      55  
      56  /* Codegen will consist of splat and shift instructions.
      57     If folding is enabled, the vec_sl tests using vector long long type will
      58     generate a lvx instead of a vspltisw+vsld pair.  */
      59  
      60  /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */
      61  /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */
      62  /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 0 } } */
      63