1  /* PR86731.  Verify that the rs6000 gimple-folding code handles the
       2     left shift operation properly.  This is a testcase variation that
       3     explicitly specifies -fwrapv, which is a condition for the
       4     gimple folding of the vec_sl() intrinsic.  */
       5  
       6  /* specify -mpower8-vector, which provides vec_sl(long long,...) support. */
       7  
       8  /* { dg-do compile } */
       9  /* { dg-require-effective-target powerpc_p8vector_ok } */
      10  /* { dg-require-effective-target lp64 } */
      11  /* { dg-options "-maltivec -O3 -fwrapv -mpower8-vector " } */
      12  
      13  #include <altivec.h>
      14  
      15  vector unsigned long long splatu4(void)
      16  {
      17          vector unsigned long long mzero = {-1,-1};
      18          return (vector unsigned long long) vec_sl(mzero, mzero);
      19  }
      20  
      21  vector signed long long splats4(void)
      22  {
      23          vector unsigned long long mzero = {-1,-1};
      24          return (vector signed long long) vec_sl(mzero, mzero);
      25  }
      26  
      27  /* Codegen will consist of splat and shift instructions for most types.  If
      28     folding is enabled, the vec_sl tests using vector long long type will
      29     generate a lvx instead of a vspltisw+vsld pair.  On power10, it will
      30     generate a xxspltidp instruction instead of the lvx.  */
      31  
      32  /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
      33  /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
      34  /* { dg-final { scan-assembler-times {\mp?lxv\M|\mlvx\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
      35