1  /* PR target/83862.c */
       2  /* { dg-do compile { target { powerpc*-*-* && lp64 } } } */
       3  /* { dg-require-effective-target ppc_float128_sw } */
       4  /* { dg-require-effective-target powerpc_p8vector_ok } */
       5  /* { dg-options "-mpower8-vector -O2 -mabi=ieeelongdouble -Wno-psabi" } */
       6  
       7  /* On little endian systems, optimizing signbit of IEEE 128-bit values from
       8     memory could abort if the memory address was indexed (reg+reg).  The
       9     optimization is only on 64-bit machines with direct move.
      10  
      11     Compile with -g -O2 -mabi=ieeelongdouble -Wno-psabi.  */
      12  
      13  #ifndef TYPE
      14  #define TYPE long double
      15  #endif
      16  
      17  int sbr (TYPE a) { return __builtin_signbit (a); }
      18  int sbm (TYPE *a) { return __builtin_signbit (*a); }
      19  int sbo (TYPE *a) { return __builtin_signbit (a[4]); }
      20  int sbi (TYPE *a, unsigned long n) { return __builtin_signbit (a[n]); }
      21  void sbs (int *p, TYPE a) { *p = __builtin_signbit (a); }
      22  
      23  /* On big endian systems, this will generate 2 LDs and 1 LDX, while on
      24     little endian systems, this will generate 3 LDs and an ADD.  */
      25  
      26  /* { dg-final { scan-assembler-times {\mldx?\M}    3 } } */
      27  /* { dg-final { scan-assembler-times {\mmfvsrd\M}  2 } } */
      28  /* { dg-final { scan-assembler-times {\msrdi\M}    5 } } */
      29  /* { dg-final { scan-assembler-not   {\mmfvsrld\M}   } } */
      30  /* { dg-final { scan-assembler-not   {\mstxvx?\M}    } } */
      31  /* { dg-final { scan-assembler-not   {\mstxvw4x\M}   } } */
      32  /* { dg-final { scan-assembler-not   {\mstxvd2x\M}   } } */
      33  /* { dg-final { scan-assembler-not   {\mstvx\M}      } } */
      34