1  /* Test for reload ICE arising from POWER9 Vector Dform code generation.  */
       2  /* { dg-do compile } */
       3  /* { dg-require-effective-target powerpc_p9vector_ok } */
       4  /* { dg-options "-O1 -mpower9-vector" } */
       5  
       6  typedef __attribute__((altivec(vector__))) int type_t;
       7  type_t
       8  func (type_t *src)
       9  {
      10    asm volatile ("# force the base reg on the load below to be spilled"
      11                     : /* no outputs */
      12                     : /* no inputs */
      13                     : "r0", "r3", "r4", "r5", "r6", "r7",
      14                       "r8", "r9", "r10", "r11", "r12", "r14", "r15",
      15                       "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
      16                       "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31");
      17    return src[1];
      18  }
      19