1  /* { dg-do compile { target lp64 } } */
       2  /* { dg-require-effective-target powerpc_p9vector_ok } */
       3  /* { dg-options "-mdejagnu-cpu=power9 -O2" } */
       4  
       5  /* Test that under ISA 3.0 (-mcpu=power9), the compiler optimizes conversion to
       6     double after a vec_extract to use the VEXTRACTU{B,H} or XXEXTRACTUW
       7     instructions (which leaves the result in a vector register), and not the
       8     VEXTU{B,H,W}{L,R}X instructions (which needs a direct move to do the floating
       9     point conversion).  */
      10  
      11  #include <altivec.h>
      12  
      13  double
      14  fpcvt_int_0 (vector int a)
      15  {
      16    int c = 0;
      17    int b = vec_extract (a, c);
      18    return (double)b;
      19  }
      20  
      21  double
      22  fpcvt_int_3 (vector int a)
      23  {
      24    int c = 3;
      25    int b = vec_extract (a, c);
      26    return (double)b;
      27  }
      28  
      29  double
      30  fpcvt_uint_0 (vector unsigned int a)
      31  {
      32    int c = 0;
      33    unsigned int b = vec_extract (a, c);
      34    return (double)b;
      35  }
      36  
      37  double
      38  fpcvt_uint_3 (vector unsigned int a)
      39  {
      40    int c = 3;
      41    unsigned int b = vec_extract (a, c);
      42    return (double)b;
      43  }
      44  
      45  double
      46  fpcvt_short_0 (vector short a)
      47  {
      48    int c = 0;
      49    short b = vec_extract (a, c);
      50    return (double)b;
      51  }
      52  
      53  double
      54  fpcvt_short_7 (vector short a)
      55  {
      56    int c = 7;
      57    short b = vec_extract (a, c);
      58    return (double)b;
      59  }
      60  
      61  double
      62  fpcvt_ushort_0 (vector unsigned short a)
      63  {
      64    int c = 0;
      65    unsigned short b = vec_extract (a, c);
      66    return (double)b;
      67  }
      68  
      69  double
      70  fpcvt_ushort_7 (vector unsigned short a)
      71  {
      72    int c = 7;
      73    unsigned short b = vec_extract (a, c);
      74    return (double)b;
      75  }
      76  
      77  double
      78  fpcvt_schar_0 (vector signed char a)
      79  {
      80    int c = 0;
      81    signed char b = vec_extract (a, c);
      82    return (double)b;
      83  }
      84  
      85  double
      86  fpcvt_schar_15 (vector signed char a)
      87  {
      88    int c = 15;
      89    signed char b = vec_extract (a, c);
      90    return (double)b;
      91  }
      92  
      93  double
      94  fpcvt_uchar_0 (vector unsigned char a)
      95  {
      96    int c = 0;
      97    unsigned char b = vec_extract (a, c);
      98    return (double)b;
      99  }
     100  
     101  double
     102  fpcvt_uchar_15 (vector unsigned char a)
     103  {
     104    int c = 15;
     105    signed char b = vec_extract (a, c);
     106    return (double)b;
     107  }
     108  
     109  /* { dg-final { scan-assembler     "vextractu\[bh\] "    } } */
     110  /* { dg-final { scan-assembler     "vexts\[bh\]2d "      } } */
     111  /* { dg-final { scan-assembler     "vspltw "             } } */
     112  /* { dg-final { scan-assembler     "xscvsxddp "          } } */
     113  /* { dg-final { scan-assembler     "xvcvsxwdp "          } } */
     114  /* { dg-final { scan-assembler     "xvcvuxwdp "          } } */
     115  /* { dg-final { scan-assembler-not "exts\[bhw\] "        } } */
     116  /* { dg-final { scan-assembler-not "stxv"                } } */
     117  /* { dg-final { scan-assembler-not "m\[ft\]vsrd "        } } */
     118  /* { dg-final { scan-assembler-not "m\[ft\]vsrw\[az\] "  } } */
     119  /* { dg-final { scan-assembler-not "l\[hw\]\[az\] "      } } */