1  /* { dg-require-effective-target power10_ok } */
       2  /* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */
       3  
       4  /* Test vectorizer can exploit ISA 3.1 instruction vmulld (Vector Multiply
       5     Low Doubleword) for both signed and unsigned doubleword multiplication.  */
       6  
       7  #define N 128
       8  
       9  extern signed long long sd_a[N], sd_b[N], sd_c[N];
      10  extern unsigned long long ud_a[N], ud_b[N], ud_c[N];
      11  
      12  __attribute__ ((noipa)) void
      13  test_sd ()
      14  {
      15    for (int i = 0; i < N; i++)
      16      sd_c[i] = sd_a[i] * sd_b[i];
      17  }
      18  
      19  __attribute__ ((noipa)) void
      20  test_ud ()
      21  {
      22    for (int i = 0; i < N; i++)
      23      ud_c[i] = ud_a[i] * ud_b[i];
      24  }
      25  
      26  /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 2 "vect" } } */
      27  /* { dg-final { scan-assembler-times {\mvmulld\M} 2 } } */