1  /* Verify that overloaded built-ins for vec_insert() with short
       2     inputs produce the right codegen.  Power8 variant.  */
       3  
       4  /* { dg-do compile } */
       5  /* { dg-require-effective-target powerpc_p8vector_ok } */
       6  /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
       7  
       8  #include <altivec.h>
       9  
      10  vector bool short
      11  testbs_var(unsigned short x, vector bool short v, signed int i)
      12  {
      13     return vec_insert(x, v, i);
      14  }
      15  vector signed short
      16  testss_var(signed short x, vector signed short v, signed int i)
      17  {
      18     return vec_insert(x, v, i);
      19  }
      20  vector unsigned short
      21  testus1_var(signed short x, vector unsigned short v, signed int i)
      22  {
      23     return vec_insert(x, v, i);
      24  }
      25  vector unsigned short
      26  testus2_var(unsigned short x, vector unsigned short v, signed int i)
      27  {
      28     return vec_insert(x, v, i);
      29  }
      30  vector bool short
      31  testbs_cst(signed short x, vector bool short v)
      32  {
      33     return vec_insert(x, v, 12);
      34  }
      35  vector signed short
      36  testss_cst(signed short x, vector signed short v)
      37  {
      38     return vec_insert(x, v, 12);
      39  }
      40  vector unsigned short
      41  testus1_cst(signed short x, vector unsigned short v)
      42  {
      43     return vec_insert(x, v, 12);
      44  }
      45  vector unsigned short
      46  testus2_cst(unsigned short x, vector unsigned short v)
      47  {
      48     return vec_insert(x, v, 12);
      49  }
      50  
      51  /* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 8 { target le } } } */
      52  /* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 4 { target {  be && lp64 } } } } */
      53  /* stores.. 0 per variable tests, 1 each per cst test. */
      54  /* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 4 { target lp64 } } } */
      55  
      56  /* { dg-final { scan-assembler-times {\mlvehx\M} 4 } } */
      57  /* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
      58  
      59  /* { dg-final { scan-assembler-times {\mlhz\M|\mlvx\M|\mlxv\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
      60  /* { dg-final { scan-assembler-times {\msthx\M|\mstvx\M|\msth\M|\mstxvw4x\M} 4 { target ilp32 } } } */
      61  /* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
      62