1  /* Verify that overloaded built-ins for vec_insert() with int
       2     inputs produce the right codegen.  Power8 variant.  */
       3  
       4  /* { dg-do compile } */
       5  /* { dg-require-effective-target powerpc_p8vector_ok } */
       6  /* { dg-options "-O2 -mdejagnu-cpu=power8" } */
       7  
       8  #include <altivec.h>
       9  
      10  vector bool int
      11  testbi_var(unsigned int x, vector bool int v, signed int i)
      12  {
      13     return vec_insert(x, v, i);
      14  }
      15  vector signed int
      16  testsi_var(signed int x, vector signed int v, signed int i)
      17  {
      18     return vec_insert(x, v, i);
      19  }
      20  vector unsigned int
      21  testui1_var(signed int x, vector unsigned int v, signed int i)
      22  {
      23     return vec_insert(x, v, i);
      24  }
      25  vector unsigned int
      26  testui2_var(unsigned int x, vector unsigned int v, signed int i)
      27  {
      28     return vec_insert(x, v, i);
      29  }
      30  vector bool int
      31  testbi_cst(unsigned int x, vector bool int v)
      32  {
      33     return vec_insert(x, v, 12);
      34  }
      35  vector signed int
      36  testsi_cst(signed int x, vector signed int v)
      37  {
      38     return vec_insert(x, v, 12);
      39  }
      40  vector unsigned int
      41  testui1_cst(signed int x, vector unsigned int v)
      42  {
      43     return vec_insert(x, v, 12);
      44  }
      45  vector unsigned int
      46  testui2_cst(unsigned int x, vector unsigned int v)
      47  {
      48     return vec_insert(x, v, 12);
      49  }
      50  
      51  /* Each test has lvx (8).  cst tests have additional lvewx. (4) */
      52  /* var tests have no stwx and stvx.  cst tests have stw (4).*/
      53  /* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 { target lp64 } } } */
      54  /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 8 { target le } } } */
      55  /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && lp64 } } } } */
      56  
      57  /* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target lp64 } } } */
      58  /* { dg-final { scan-assembler-times {\mvperm\M} 12 { target lp64 } } } */
      59  
      60  /* { dg-final { scan-assembler-times {\mvperm\M} 12 { target ilp32 } } } */
      61  /* { dg-final { scan-assembler-times {\mstvx\M|\mstwx\M|\mstw\M|\mstxvw4x\M} 4 { target ilp32 } } } */
      62  /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvw4x\M} 4 { target { be && ilp32 } } } } */
      63  /* { dg-final { scan-assembler-times {\mlvewx\M} 4 { target ilp32 } } } */