1  /* Verify that overloaded built-ins for vec_extract() with short
       2     inputs produce the right results with a P8 (LE or BE) target.  */
       3  
       4  /* { dg-do compile } */
       5  /* { dg-require-effective-target powerpc_p8vector_ok } */
       6  /* { dg-options "-mdejagnu-cpu=power8 -O2" } */
       7  
       8  // six tests total. Targeting P8, both LE and BE.
       9  // p8 (le) variable offset: rldicl, subfic, sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh/2:rlwinm)
      10  // p8 (le) const offset:                          mtvsrd,                                (1:extsh/2:rlwinm)
      11  // p8 (be) var offset:                      sldi, mtvsrd, xxpermdi, vslo, mfvsrd, srdi, (1:extsh:2:rlwinm)
      12  // p8 (be) const offset:    vsplth,               mfvsrd,                                (1:extsh/2:rlwinm)
      13  
      14  // * - each of the above will have an extsh if the argument is signed.
      15  // * - bool and unsigned tests also have an rlwinm.
      16  
      17  /* { dg-final { scan-assembler-times "rldicl" 3 {target { lp64 && le } } } } */
      18  /* { dg-final { scan-assembler-times "subfic" 3 {target { lp64 && le } } } } */
      19  /* { dg-final { scan-assembler-times "vsplth" 3 { target { lp64 && be } } } } */
      20  /* { dg-final { scan-assembler-times "sldi" 3 { target lp64 } } } */
      21  /* { dg-final { scan-assembler-times "mtvsrd" 3 { target lp64 } } } */
      22  /* { dg-final { scan-assembler-times "xxpermdi" 3 { target lp64 } } } */
      23  /* { dg-final { scan-assembler-times "vslo" 3 { target lp64 } } } */
      24  /* { dg-final { scan-assembler-times "mfvsrd" 6 { target lp64 } } } */
      25  /* { dg-final { scan-assembler-times "srdi" 3 { target lp64 } } } */
      26  /* { dg-final { scan-assembler-times "extsh" 2 { target lp64 } } } */
      27  /* { dg-final { scan-assembler-times "rlwinm" 4 { target lp64 } } } */
      28  
      29  /* -m32 codegen tests. */
      30  /* { dg-final { scan-assembler-times {\mli\M} 6 { target ilp32 } } } */
      31  /* { dg-final { scan-assembler-times "stxvw4x" 6 { target ilp32 } } } */
      32  /* add and rlwinm instructions only on the variable tests. */
      33  /* { dg-final { scan-assembler-times {\madd\M} 3 { target ilp32 } } } */
      34  /* { dg-final { scan-assembler-times "rlwinm" 3 { target ilp32 } } } */
      35  /* { dg-final { scan-assembler-times {\maddi\M} 9 { target ilp32 } } } */
      36  /* { dg-final { scan-assembler-times {\mlha\M|\mlhz\M} 6 { target ilp32 } } } */
      37  
      38  
      39  #include <altivec.h>
      40  
      41  unsigned short
      42  testbi_cst (vector bool short vbs2)
      43  {
      44    return vec_extract (vbs2, 12);
      45  }
      46  
      47  signed short
      48  testsi_cst (vector signed short vss2)
      49  {
      50    return vec_extract (vss2, 12);
      51  }
      52  
      53  unsigned short
      54  testui_cst12 (vector unsigned short vus2)
      55  {
      56    return vec_extract (vus2, 12);
      57  }
      58  
      59  unsigned short
      60  testbi_var (vector bool short vbs2, signed int si)
      61  {
      62    return vec_extract (vbs2, si);
      63  }
      64  
      65  signed short
      66  testsi_var (vector signed short vss2, signed int si)
      67  {
      68  return vec_extract (vss2, si);
      69  }
      70  
      71  unsigned short
      72  testui_var (vector unsigned short vus2, signed int si)
      73  {
      74  return vec_extract (vus2, si);
      75  }
      76